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Fix a crash that Andrew noticed, and add a pair of braces to unfconfuse 

XCode's indenting.

llvm-svn: 24159
This commit is contained in:
Nate Begeman 2005-11-02 18:42:59 +00:00
parent 662295587d
commit ee065281e8
1 changed files with 5 additions and 5 deletions
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10
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -963,14 +963,14 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
} }
// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
unsigned ExtendBits = unsigned ExtendBits =
MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) if (ExtendBits == 64 || (N1C->getValue() & (~0ULL << ExtendBits) == 0))
return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
} }
// fold (and (or x, 0xFFFF), 0xFF) -> 0xFF // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
if (N0.getOpcode() == ISD::OR && N1C) if (N1C && N0.getOpcode() == ISD::OR)
if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
return N1; return N1;
@ -1031,7 +1031,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
} }
// fold (and (sra)) -> (and (srl)) when possible. // fold (and (sra)) -> (and (srl)) when possible.
if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) {
if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
// If the RHS of the AND has zeros where the sign bits of the SRA will // If the RHS of the AND has zeros where the sign bits of the SRA will
// land, turn the SRA into an SRL. // land, turn the SRA into an SRL.
@ -1043,7 +1043,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
return SDOperand(); return SDOperand();
} }
} }
}
// fold (zext_inreg (extload x)) -> (zextload x) // fold (zext_inreg (extload x)) -> (zextload x)
if (N0.getOpcode() == ISD::EXTLOAD) { if (N0.getOpcode() == ISD::EXTLOAD) {
MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();