forked from OSchip/llvm-project
Fix a crash that Andrew noticed, and add a pair of braces to unfconfuse
XCode's indenting. llvm-svn: 24159
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@ -963,14 +963,14 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
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}
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// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
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if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
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if (N1C && N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
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unsigned ExtendBits =
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MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
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if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
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if (ExtendBits == 64 || (N1C->getValue() & (~0ULL << ExtendBits) == 0))
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return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
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}
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// fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
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if (N0.getOpcode() == ISD::OR && N1C)
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if (N1C && N0.getOpcode() == ISD::OR)
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if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
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if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
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return N1;
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@ -1031,7 +1031,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
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}
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// fold (and (sra)) -> (and (srl)) when possible.
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if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse())
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if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) {
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if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
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// If the RHS of the AND has zeros where the sign bits of the SRA will
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// land, turn the SRA into an SRL.
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@ -1043,7 +1043,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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return SDOperand();
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}
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}
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}
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// fold (zext_inreg (extload x)) -> (zextload x)
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if (N0.getOpcode() == ISD::EXTLOAD) {
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MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
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