From ede9d861db03fbd46ad131af6d1c01039674abaf Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Fri, 29 Oct 2010 19:56:07 +0000 Subject: [PATCH] Covert this test to .s form. llvm-svn: 117694 --- llvm/test/MC/ARM/neon-neg-encoding.ll | 107 -------------------------- llvm/test/MC/ARM/neon-neg-encoding.s | 30 ++++++++ 2 files changed, 30 insertions(+), 107 deletions(-) delete mode 100644 llvm/test/MC/ARM/neon-neg-encoding.ll create mode 100644 llvm/test/MC/ARM/neon-neg-encoding.s diff --git a/llvm/test/MC/ARM/neon-neg-encoding.ll b/llvm/test/MC/ARM/neon-neg-encoding.ll deleted file mode 100644 index ec741cadc32e..000000000000 --- a/llvm/test/MC/ARM/neon-neg-encoding.ll +++ /dev/null @@ -1,107 +0,0 @@ -; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s - -define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3] - %tmp2 = sub <8 x i8> zeroinitializer, %tmp1 - ret <8 x i8> %tmp2 -} - -define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vneg.s16 d16, d16 @ encoding: [0xa0,0x03,0xf5,0xf3 - %tmp2 = sub <4 x i16> zeroinitializer, %tmp1 - ret <4 x i16> %tmp2 -} - -define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vneg.s32 d16, d16 @ encoding: [0xa0,0x03,0xf9,0xf3] - %tmp2 = sub <2 x i32> zeroinitializer, %tmp1 - ret <2 x i32> %tmp2 -} - -define <2 x float> @vnegf32(<2 x float>* %A) nounwind { - %tmp1 = load <2 x float>* %A -; CHECK: vneg.f32 d16, d16 @ encoding: [0xa0,0x07,0xf9,0xf3] - %tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1 - ret <2 x float> %tmp2 -} - -define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vneg.s8 q8, q8 @ encoding: [0xe0,0x03,0xf1,0xf3] - %tmp2 = sub <16 x i8> zeroinitializer, %tmp1 - ret <16 x i8> %tmp2 -} - -define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vneg.s16 q8, q8 @ encoding: [0xe0,0x03,0xf5,0xf3] - %tmp2 = sub <8 x i16> zeroinitializer, %tmp1 - ret <8 x i16> %tmp2 -} - -define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vneg.s32 q8, q8 @ encoding: [0xe0,0x03,0xf9,0xf3] - %tmp2 = sub <4 x i32> zeroinitializer, %tmp1 - ret <4 x i32> %tmp2 -} - -define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { - %tmp1 = load <4 x float>* %A -; CHECK: vneg.f32 q8, q8 @ encoding: [0xe0,0x07,0xf9,0xf3] - %tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1 - ret <4 x float> %tmp2 -} - -define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind { - %tmp1 = load <8 x i8>* %A -; CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xf3] - %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1) - ret <8 x i8> %tmp2 -} - -define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind { - %tmp1 = load <4 x i16>* %A -; CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xf3] - %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1) - ret <4 x i16> %tmp2 -} - -define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind { - %tmp1 = load <2 x i32>* %A -; CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3] - %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1) - ret <2 x i32> %tmp2 -} - -define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind { - %tmp1 = load <16 x i8>* %A -; CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xf3] - %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1) - ret <16 x i8> %tmp2 -} - -define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind { - %tmp1 = load <8 x i16>* %A -; CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xf3] - %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1) - ret <8 x i16> %tmp2 -} - -define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind { - %tmp1 = load <4 x i32>* %A -; CHECK: vqneg.s32 q8, q8 @ encoding: [0xe0,0x07,0xf8,0xf3] - %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1) - ret <4 x i32> %tmp2 -} - -declare <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32>) nounwind readnone - -declare <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8>) nounwind readnone -declare <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16>) nounwind readnone -declare <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32>) nounwind readnone diff --git a/llvm/test/MC/ARM/neon-neg-encoding.s b/llvm/test/MC/ARM/neon-neg-encoding.s new file mode 100644 index 000000000000..b81f49bcf921 --- /dev/null +++ b/llvm/test/MC/ARM/neon-neg-encoding.s @@ -0,0 +1,30 @@ +// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s + +// CHECK: vneg.s8 d16, d16 @ encoding: [0xa0,0x03,0xf1,0xf3] + vneg.s8 d16, d16 +// CHECK: vneg.s16 d16, d16 @ encoding: [0xa0,0x03,0xf5,0xf3] + vneg.s16 d16, d16 +// CHECK: vneg.s32 d16, d16 @ encoding: [0xa0,0x03,0xf9,0xf3] + vneg.s32 d16, d16 +// CHECK: vneg.f32 d16, d16 @ encoding: [0xa0,0x07,0xf9,0xf3] + vneg.f32 d16, d16 +// CHECK: vneg.s8 q8, q8 @ encoding: [0xe0,0x03,0xf1,0xf3] + vneg.s8 q8, q8 +// CHECK: vneg.s16 q8, q8 @ encoding: [0xe0,0x03,0xf5,0xf3] + vneg.s16 q8, q8 +// CHECK: vneg.s32 q8, q8 @ encoding: [0xe0,0x03,0xf9,0xf3] + vneg.s32 q8, q8 +// CHECK: vneg.f32 q8, q8 @ encoding: [0xe0,0x07,0xf9,0xf3] + vneg.f32 q8, q8 +// CHECK: vqneg.s8 d16, d16 @ encoding: [0xa0,0x07,0xf0,0xf3] + vqneg.s8 d16, d16 +// CHECK: vqneg.s16 d16, d16 @ encoding: [0xa0,0x07,0xf4,0xf3] + vqneg.s16 d16, d16 +// CHECK: vqneg.s32 d16, d16 @ encoding: [0xa0,0x07,0xf8,0xf3] + vqneg.s32 d16, d16 +// CHECK: vqneg.s8 q8, q8 @ encoding: [0xe0,0x07,0xf0,0xf3] + vqneg.s8 q8, q8 +// CHECK: vqneg.s16 q8, q8 @ encoding: [0xe0,0x07,0xf4,0xf3] + vqneg.s16 q8, q8 +// CHECK: vqneg.s32 q8, q8 @ encoding: [0xe0,0x07,0xf8,0xf3] + vqneg.s32 q8, q8