forked from OSchip/llvm-project
[AMDGPU][MC][GFX10] Enabled v_movrel*[sdwa|dpp|dpp8] opcodes
See https://bugs.llvm.org/show_bug.cgi?id=43712 Reviewers: arsenm, rampitec Differential Revision: https://reviews.llvm.org/D70170
This commit is contained in:
Dmitry Preobrazhensky
parent
b622ff39c0
commit
edd9f70163
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@ -1320,6 +1320,7 @@ private:
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bool validateIntClampSupported(const MCInst &Inst);
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bool validateMIMGAtomicDMask(const MCInst &Inst);
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bool validateMIMGGatherDMask(const MCInst &Inst);
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bool validateMovrels(const MCInst &Inst);
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bool validateMIMGDataSize(const MCInst &Inst);
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bool validateMIMGAddrSize(const MCInst &Inst);
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bool validateMIMGD16(const MCInst &Inst);
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@ -3049,6 +3050,41 @@ bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {
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return DMask == 0x1 || DMask == 0x2 || DMask == 0x4 || DMask == 0x8;
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}
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static bool IsMovrelsSDWAOpcode(const unsigned Opcode)
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{
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switch (Opcode) {
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case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:
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case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:
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case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:
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return true;
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default:
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return false;
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}
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}
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// movrels* opcodes should only allow VGPRS as src0.
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// This is specified in .td description for vop1/vop3,
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// but sdwa is handled differently. See isSDWAOperand.
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bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst) {
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const unsigned Opc = Inst.getOpcode();
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const MCInstrDesc &Desc = MII.get(Opc);
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if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 || !IsMovrelsSDWAOpcode(Opc))
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return true;
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const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
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assert(Src0Idx != -1);
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const MCOperand &Src0 = Inst.getOperand(Src0Idx);
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if (!Src0.isReg())
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return false;
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auto Reg = Src0.getReg();
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const MCRegisterInfo *TRI = getContext().getRegisterInfo();
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return !isSGPR(mc2PseudoReg(Reg), TRI);
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}
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bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
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const unsigned Opc = Inst.getOpcode();
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@ -3469,6 +3505,10 @@ bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
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"invalid image_gather dmask: only one bit must be set");
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return false;
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}
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if (!validateMovrels(Inst)) {
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Error(IDLoc, "source operand must be a VGPR");
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return false;
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}
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if (!validateFlatOffset(Inst, Operands)) {
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return false;
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}
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@ -260,14 +260,9 @@ defm V_CLREXCP : VOP1Inst <"v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
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}
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// Restrict src0 to be VGPR
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def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> {
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def VOP_MOVRELS : VOPProfile<[i32, i32, untyped, untyped]> {
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let Src0RC32 = VRegSrc_32;
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let Src0RC64 = VRegSrc_32;
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let HasExt = 0;
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let HasExtDPP = 0;
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let HasExtSDWA = 0;
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let HasExtSDWA9 = 0;
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}
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// Special case because there are no true output operands. Hack vdst
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@ -281,26 +276,24 @@ class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, un
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let Outs = (outs);
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let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
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let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
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let InsDPP = (ins DstRC:$vdst, DstRC:$old, Src0RC32:$src0,
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dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
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bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
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let InsDPP16 = !con(InsDPP, (ins FI:$fi));
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let InsSDWA = (ins Src0RC32:$vdst, Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
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clampmod:$clamp, omod:$omod, dst_sel:$dst_sel, dst_unused:$dst_unused,
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src0_sel:$src0_sel);
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let Asm32 = getAsm32<1, 1>.ret;
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let Asm64 = getAsm64<1, 1, 0, 0, 1>.ret;
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let AsmDPP = getAsmDPP<1, 1, 0>.ret;
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let AsmDPP16 = getAsmDPP16<1, 1, 0>.ret;
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let AsmSDWA = getAsmSDWA<1, 1>.ret;
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let OutsSDWA = (outs Src0RC32:$vdst);
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let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
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clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
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src0_sel:$src0_sel);
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let AsmSDWA9 = getAsmSDWA9<1, 0, 1>.ret;
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let HasExt = 0;
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let HasExtDPP = 0;
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let HasExtSDWA = 0;
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let HasExtSDWA9 = 0;
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let OutsDPP = (outs Src0RC32:$vdst);
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let InsDPP16 = (ins Src0RC32:$old, Src0RC32:$src0,
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dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
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bank_mask:$bank_mask, bound_ctrl:$bound_ctrl, FI:$fi);
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let AsmDPP16 = getAsmDPP16<1, 1, 0>.ret;
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let OutsDPP8 = (outs Src0RC32:$vdst);
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let InsDPP8 = (ins Src0RC32:$old, Src0RC32:$src0, dpp8:$dpp8, FI:$fi);
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let AsmDPP8 = getAsmDPP8<1, 1, 0>.ret;
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let HasDst = 0;
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let EmitDst = 1; // force vdst emission
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@ -310,14 +303,14 @@ def VOP_MOVRELD : VOP_MOVREL<VSrc_b32>;
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def VOP_MOVRELSD : VOP_MOVREL<VRegSrc_32>;
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let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
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// v_movreld_b32 is a special case because the destination output
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// v_movreld_b32 is a special case because the destination output
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// register is really a source. It isn't actually read (but may be
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// written), and is only to provide the base register to start
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// indexing from. Tablegen seems to not let you define an implicit
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// virtual register output for the super register being written into,
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// so this must have an implicit def of the register added to it.
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defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;
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defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>;
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defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_MOVRELS>;
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defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>;
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} // End Uses = [M0, EXEC]
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@ -528,16 +521,10 @@ let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
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}
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} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
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multiclass VOP1_Real_gfx10_no_dpp<bits<9> op> :
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VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
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VOP1_Real_sdwa_gfx10<op>;
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multiclass VOP1_Real_gfx10_no_dpp8<bits<9> op> :
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VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
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VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>;
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multiclass VOP1_Real_gfx10<bits<9> op> :
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VOP1_Real_gfx10_no_dpp8<op>, VOP1_Real_dpp8_gfx10<op>;
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VOP1_Real_e32_gfx10<op>, VOP1_Real_e64_gfx10<op>,
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VOP1_Real_sdwa_gfx10<op>, VOP1_Real_dpp_gfx10<op>,
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VOP1_Real_dpp8_gfx10<op>;
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defm V_PIPEFLUSH : VOP1_Real_gfx10<0x01b>;
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defm V_MOVRELSD_2_B32 : VOP1_Real_gfx10<0x048>;
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@ -620,12 +607,6 @@ multiclass VOP1_Real_gfx6_gfx7<bits<9> op> :
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multiclass VOP1_Real_gfx6_gfx7_gfx10<bits<9> op> :
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VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10<op>;
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multiclass VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<bits<9> op> :
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VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10_no_dpp8<op>;
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multiclass VOP1_Real_gfx6_gfx7_gfx10_no_dpp<bits<9> op> :
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VOP1_Real_gfx6_gfx7<op>, VOP1_Real_gfx10_no_dpp<op>;
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defm V_LOG_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x026>;
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defm V_RCP_CLAMP_F32 : VOP1_Real_gfx6_gfx7<0x028>;
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defm V_RCP_LEGACY_F32 : VOP1_Real_gfx6_gfx7<0x029>;
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@ -683,9 +664,9 @@ defm V_FRACT_F64 : VOP1_Real_gfx6_gfx7_gfx10<0x03e>;
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defm V_FREXP_EXP_I32_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x03f>;
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defm V_FREXP_MANT_F32 : VOP1_Real_gfx6_gfx7_gfx10<0x040>;
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defm V_CLREXCP : VOP1_Real_gfx6_gfx7_gfx10<0x041>;
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defm V_MOVRELD_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp<0x042>;
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defm V_MOVRELS_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<0x043>;
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defm V_MOVRELSD_B32 : VOP1_Real_gfx6_gfx7_gfx10_no_dpp8<0x044>;
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defm V_MOVRELD_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x042>;
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defm V_MOVRELS_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x043>;
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defm V_MOVRELSD_B32 : VOP1_Real_gfx6_gfx7_gfx10<0x044>;
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//===----------------------------------------------------------------------===//
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// GFX8, GFX9 (VI).
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@ -32163,6 +32163,18 @@ v_movreld_b32_e64 v5, 0.5
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v_movreld_b32_e64 v5, -4.0
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// GFX10: encoding: [0x05,0x00,0xc2,0xd5,0xf7,0x00,0x00,0x00]
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v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
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v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
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v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
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v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
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v_movrels_b32 v5, v1
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// GFX10: encoding: [0x01,0x87,0x0a,0x7e]
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@ -32181,6 +32193,30 @@ v_movrels_b32_e64 v255, v1
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v_movrels_b32_e64 v5, v255
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// GFX10: encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
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v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
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v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
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v_movrels_b32_e32 v5, s1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrels_b32_e32 v5, 1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrels_b32_e64 v5, s1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrels_b32_e64 v5, 1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrels_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10-ERR: error: source operand must be a VGPR
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v_movrels_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10-ERR: error: source operand must be a VGPR
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v_movrelsd_b32 v5, v1
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// GFX10: encoding: [0x01,0x89,0x0a,0x7e]
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@ -32199,9 +32235,33 @@ v_movrelsd_b32_e64 v255, v1
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v_movrelsd_b32_e64 v5, v255
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// GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
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v_movrelsd_b32 v5, s1
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v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
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v_movrelsd_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
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v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
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v_movrelsd_b32_e32 v5, s1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_b32_e32 v5, 1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_b32_e64 v5, s1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_b32_e64 v5, 1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10-ERR: error: source operand must be a VGPR
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v_movrelsd_b32_sdwa v0, 1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10-ERR: error: source operand must be a VGPR
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v_movrelsd_2_b32 v5, v1
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// GFX10: encoding: [0x01,0x91,0x0a,0x7e]
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@ -32220,9 +32280,36 @@ v_movrelsd_2_b32_e64 v255, v1
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v_movrelsd_2_b32_e64 v5, v255
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// GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
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v_movrelsd_2_b32 v5, s1
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v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
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v_movrelsd_2_b32_sdwa v0, v0 dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
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v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10: encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
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v_movrelsd_2_b32_e32 v5, s1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_2_b32_e32 v5, 1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_2_b32_e64 v5, s1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_2_b32_e64 v5, 1
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// GFX10-ERR: error: invalid operand for instruction
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v_movrelsd_2_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10-ERR: error: source operand must be a VGPR
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v_movrelsd_2_b32_sdwa v0, 0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10-ERR: error: source operand must be a VGPR
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v_movrelsd_2_b32_sdwa v0, null dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD
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// GFX10-ERR: error: source operand must be a VGPR
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v_cvt_f16_u16_e32 v5, v1
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// GFX10: encoding: [0x01,0xa1,0x0a,0x7e]
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@ -680,3 +680,15 @@ v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x1 bank_mask:0x0
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v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
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// GFX10: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
|
||||
|
||||
v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
|
||||
// GFX10: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00]
|
||||
|
||||
v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1
|
||||
// GFX10: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00]
|
||||
|
||||
v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
|
||||
// GFX10: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00]
|
||||
|
||||
v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0
|
||||
// GFX10: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00]
|
||||
|
|
|
|||
|
|
@ -577,3 +577,15 @@ v_mac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0]
|
|||
|
||||
v_mac_f32 v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1
|
||||
// GFX10: v_mac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05]
|
||||
|
||||
v_movreld_b32 v0, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1
|
||||
// GFX10: [0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05]
|
||||
|
||||
v_movrels_b32 v0, v2 dpp8:[0,0,0,0,0,0,0,0]
|
||||
// GFX10: [0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00]
|
||||
|
||||
v_movrelsd_2_b32 v0, v255 dpp8:[7,6,5,4,3,2,1,0]
|
||||
// GFX10: [0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05]
|
||||
|
||||
v_movrelsd_b32 v0, v2 dpp8:[7,6,5,4,3,2,1,0]
|
||||
// GFX10: [0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05]
|
||||
|
|
|
|||
|
|
@ -86292,6 +86292,18 @@
|
|||
# GFX10: v_movreld_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00]
|
||||
0x05,0x00,0xc2,0xd5,0xff,0x01,0x00,0x00
|
||||
|
||||
# GFX10: v_movreld_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00]
|
||||
0xf9,0x84,0x00,0x7e,0x02,0x06,0x06,0x00
|
||||
|
||||
# GFX10: v_movreld_b32_sdwa v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00]
|
||||
0xf9,0x84,0x00,0x7e,0x02,0x06,0x86,0x00
|
||||
|
||||
# GFX10: v_movreld_b32_sdwa v0, 64 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00]
|
||||
0xf9,0x84,0x00,0x7e,0xc0,0x06,0x86,0x00
|
||||
|
||||
# GFX10: v_movreld_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00]
|
||||
0xf9,0x84,0x00,0x7e,0x00,0x06,0x0e,0x00
|
||||
|
||||
# GFX10: v_movrels_b32_e32 v255, v1 ; encoding: [0x01,0x87,0xfe,0x7f]
|
||||
0x01,0x87,0xfe,0x7f
|
||||
|
||||
|
|
@ -86310,6 +86322,12 @@
|
|||
# GFX10: v_movrels_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00]
|
||||
0x05,0x00,0xc3,0xd5,0xff,0x01,0x00,0x00
|
||||
|
||||
# GFX10: v_movrels_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00]
|
||||
0xf9,0x86,0x00,0x7e,0x02,0x06,0x06,0x00
|
||||
|
||||
# GFX10: v_movrels_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00]
|
||||
0xf9,0x86,0x00,0x7e,0x00,0x06,0x0e,0x00
|
||||
|
||||
# GFX10: v_movrelsd_2_b32_e32 v255, v1 ; encoding: [0x01,0x91,0xfe,0x7f]
|
||||
0x01,0x91,0xfe,0x7f
|
||||
|
||||
|
|
@ -86328,6 +86346,15 @@
|
|||
# GFX10: v_movrelsd_2_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
|
||||
0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00
|
||||
|
||||
# GFX10: v_movrelsd_2_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00]
|
||||
0xf9,0x90,0x00,0x7e,0x02,0x06,0x06,0x00
|
||||
|
||||
# GFX10: v_movrelsd_2_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00]
|
||||
0xf9,0x90,0x00,0x7e,0x00,0x06,0x06,0x00
|
||||
|
||||
# GFX10: v_movrelsd_2_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00]
|
||||
0xf9,0x90,0x00,0x7e,0x00,0x06,0x0e,0x00
|
||||
|
||||
# GFX10: v_movrelsd_b32_e32 v255, v1 ; encoding: [0x01,0x89,0xfe,0x7f]
|
||||
0x01,0x89,0xfe,0x7f
|
||||
|
||||
|
|
@ -86346,6 +86373,15 @@
|
|||
# GFX10: v_movrelsd_b32_e64 v5, v255 ; encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
|
||||
0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00
|
||||
|
||||
# GFX10: v_movrelsd_b32_sdwa v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00]
|
||||
0xf9,0x88,0x00,0x7e,0x02,0x06,0x06,0x00
|
||||
|
||||
# GFX10: v_movrelsd_b32_sdwa v0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00]
|
||||
0xf9,0x88,0x00,0x7e,0x00,0x06,0x06,0x00
|
||||
|
||||
# GFX10: v_movrelsd_b32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00]
|
||||
0xf9,0x88,0x00,0x7e,0x00,0x06,0x0e,0x00
|
||||
|
||||
# GFX10: v_mqsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4] ; encoding: [0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04]
|
||||
0xfe,0x00,0x73,0xd5,0x01,0x05,0x0e,0x04
|
||||
|
||||
|
|
|
|||
|
|
@ -656,3 +656,15 @@
|
|||
|
||||
# GFX10: v_subrev_nc_u32_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00]
|
||||
0xfa,0x04,0x0a,0x4e,0x01,0x1b,0x04,0x00
|
||||
|
||||
# GFX10: v_movreld_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00]
|
||||
0xfa,0x84,0x02,0x7e,0x00,0x1b,0x00,0x00
|
||||
|
||||
# GFX10: v_movrels_b32_dpp v1, v0 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 fi:1 ; encoding: [0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00]
|
||||
0xfa,0x86,0x02,0x7e,0x00,0x1b,0x04,0x00
|
||||
|
||||
# GFX10: v_movrelsd_2_b32_dpp v0, v2 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00]
|
||||
0xfa,0x90,0x00,0x7e,0x02,0x1b,0x00,0x00
|
||||
|
||||
# GFX10: v_movrelsd_b32_dpp v0, v255 quad_perm:[3,2,1,0] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00]
|
||||
0xfa,0x88,0x00,0x7e,0xff,0x1b,0x00,0x00
|
||||
|
|
|
|||
|
|
@ -544,3 +544,15 @@
|
|||
|
||||
# GFX10: v_mac_f32_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05]
|
||||
0xea,0x04,0x0a,0x3e,0x01,0x77,0x39,0x05
|
||||
|
||||
# GFX10: v_movreld_b32_dpp v0, v1 dpp8:[7,6,5,4,3,2,1,0] fi:1 ; encoding: [0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05]
|
||||
0xea,0x84,0x00,0x7e,0x01,0x77,0x39,0x05
|
||||
|
||||
# GFX10: v_movrels_b32_dpp v0, v2 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00]
|
||||
0xe9,0x86,0x00,0x7e,0x02,0x00,0x00,0x00
|
||||
|
||||
# GFX10: v_movrelsd_2_b32_dpp v0, v255 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05]
|
||||
0xe9,0x90,0x00,0x7e,0xff,0x77,0x39,0x05
|
||||
|
||||
# GFX10: v_movrelsd_b32_dpp v0, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05]
|
||||
0xe9,0x88,0x00,0x7e,0x02,0x77,0x39,0x05
|
||||
|
|
|
|||
Loading…
Reference in New Issue