forked from OSchip/llvm-project
R600/SI: Avoid generating S_MOVs with 64-bit immediates v2
SITargetLowering::analyzeImmediate() was converting the 64-bit values to 32-bit and then checking if they were an inline immediate. Some of these conversions caused this check to succeed and produced S_MOV instructions with 64-bit immediates, which are illegal. v2: - Clean up logic Reviewed-by: Christian König <christian.koenig@amd.com> llvm-svn: 178927
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@ -424,9 +424,12 @@ int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
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float F;
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} Imm;
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if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N))
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if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
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if (Node->getZExtValue() >> 32) {
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return -1;
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}
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Imm.I = Node->getSExtValue();
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else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
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} else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
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Imm.F = Node->getValueAPF().convertToFloat();
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else
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return -1; // It isn't an immediate
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@ -0,0 +1,26 @@
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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; XXX: Enable once SI supports buffer stores
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; XFAIL: *
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; Use a 64-bit value with lo bits that can be represented as an inline constant
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; CHECK: @i64_imm_inline_lo
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; CHECK: S_MOV_B32 [[LO:SGPR[0-9]+]], 5
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; CHECK: V_MOV_B32_e32 [[LO_VGPR:VGPR[0-9]+]], [[LO]]
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; CHECK: BUFFER_STORE_DWORDX2 [[LO_VGPR]]_
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define void @i64_imm_inline_lo(i64 addrspace(1) *%out) {
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entry:
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store i64 1311768464867721221, i64 addrspace(1) *%out ; 0x1234567800000005
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ret void
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}
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; Use a 64-bit value with hi bits that can be represented as an inline constant
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; CHECK: @i64_imm_inline_hi
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; CHECK: S_MOV_B32 [[HI:SGPR[0-9]+]], 5
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; CHECK: V_MOV_B32_e32 [[HI_VGPR:VGPR[0-9]+]], [[HI]]
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; CHECK: BUFFER_STORE_DWORDX2 {{VGPR[0-9]+}}_[[HI_VGPR]]
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define void @i64_imm_inline_hi(i64 addrspace(1) *%out) {
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entry:
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store i64 21780256376, i64 addrspace(1) *%out ; 0x0000000512345678
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ret void
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}
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