diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 66eda3ba360c..240dad1ed5ca 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -237,8 +237,8 @@ def : ProcessorModel<"sifive-e31", RocketModel, [FeatureStdExtM,
 
 def : ProcessorModel<"sifive-u54", RocketModel, [Feature64Bit,
                                                  FeatureStdExtM,
-                                                 FeatureStdExtF,
                                                  FeatureStdExtA,
+                                                 FeatureStdExtF,
                                                  FeatureStdExtD,
                                                  FeatureStdExtC]>;