forked from OSchip/llvm-project
[PowerPC] Provide some P8-specific altivec overloads for P7
This adds additional support for XL compatibility. There are a number of functions in altivec.h that produce a single instruction (or a very short sequence) for Power8 but can be done on Power7 without scalarization. XL provides these implementations. This patch adds the following overloads for doubleword vectors: vec_add vec_cmpeq vec_cmpgt vec_cmpge vec_cmplt vec_cmple vec_sl vec_sr vec_sra
This commit is contained in:
Nemanja Ivanovic
parent
d40a0b8af7
commit
ed87f512bb
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@ -309,6 +309,26 @@ static __inline__ vector unsigned char __attribute__((__always_inline__))
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vec_add_u128(vector unsigned char __a, vector unsigned char __b) {
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return __builtin_altivec_vadduqm(__a, __b);
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}
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#elif defined(__VSX__)
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static __inline__ vector signed long long __ATTRS_o_ai
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vec_add(vector signed long long __a, vector signed long long __b) {
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vector unsigned int __res =
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(vector unsigned int)__a + (vector unsigned int)__b;
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vector unsigned int __carry = __builtin_altivec_vaddcuw(
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(vector unsigned int)__a, (vector unsigned int)__b);
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#ifdef __LITTLE_ENDIAN__
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__carry = __builtin_shufflevector(__carry, __carry, 3, 0, 1, 2);
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#else
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__carry = __builtin_shufflevector(__carry, __carry, 1, 2, 3, 0);
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#endif
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return (vector signed long long)(__res + __carry);
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}
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static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_add(vector unsigned long long __a, vector unsigned long long __b) {
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return (vector unsigned long long)vec_add((vector signed long long)__a,
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(vector signed long long)__b);
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}
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#endif // defined(__POWER8_VECTOR__) && defined(__powerpc64__)
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static __inline__ vector float __ATTRS_o_ai vec_add(vector float __a,
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@ -1730,7 +1750,31 @@ vec_cmpeq(vector bool long long __a, vector bool long long __b) {
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return (vector bool long long)__builtin_altivec_vcmpequd(
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(vector long long)__a, (vector long long)__b);
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}
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#else
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpeq(vector signed long long __a, vector signed long long __b) {
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vector bool int __wordcmp =
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vec_cmpeq((vector signed int)__a, (vector signed int)__b);
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#ifdef __LITTLE_ENDIAN__
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__wordcmp &= __builtin_shufflevector(__wordcmp, __wordcmp, 3, 0, 1, 2);
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return (vector bool long long)__builtin_shufflevector(__wordcmp, __wordcmp, 1,
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1, 3, 3);
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#else
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__wordcmp &= __builtin_shufflevector(__wordcmp, __wordcmp, 1, 2, 3, 0);
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return (vector bool long long)__builtin_shufflevector(__wordcmp, __wordcmp, 0,
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0, 2, 2);
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#endif
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}
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpeq(vector unsigned long long __a, vector unsigned long long __b) {
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return vec_cmpeq((vector signed long long)__a, (vector signed long long)__b);
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}
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpeq(vector bool long long __a, vector bool long long __b) {
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return vec_cmpeq((vector signed long long)__a, (vector signed long long)__b);
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}
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#endif
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static __inline__ vector bool int __ATTRS_o_ai vec_cmpeq(vector float __a,
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@ -2018,6 +2062,24 @@ vec_cmpne(vector unsigned long long __a, vector unsigned long long __b) {
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return (vector bool long long)
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~(__builtin_altivec_vcmpequd((vector long long)__a, (vector long long)__b));
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}
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#else
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpne(vector bool long long __a, vector bool long long __b) {
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return (vector bool long long)~(
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vec_cmpeq((vector signed long long)__a, (vector signed long long)__b));
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}
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpne(vector signed long long __a, vector signed long long __b) {
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return (vector bool long long)~(
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vec_cmpeq((vector signed long long)__a, (vector signed long long)__b));
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}
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpne(vector unsigned long long __a, vector unsigned long long __b) {
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return (vector bool long long)~(
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vec_cmpeq((vector signed long long)__a, (vector signed long long)__b));
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}
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#endif
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#ifdef __VSX__
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@ -2070,6 +2132,46 @@ static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpgt(vector unsigned long long __a, vector unsigned long long __b) {
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return (vector bool long long)__builtin_altivec_vcmpgtud(__a, __b);
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}
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#else
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpgt(vector signed long long __a, vector signed long long __b) {
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vector signed int __sgtw =
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vec_cmpgt((vector signed int)__a, (vector signed int)__b);
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vector unsigned int __ugtw =
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vec_cmpgt((vector unsigned int)__a, (vector unsigned int)__b);
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vector bool int __eqw =
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vec_cmpeq((vector signed int)__a, (vector signed int)__b);
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#ifdef __LITTLE_ENDIAN__
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__ugtw = __builtin_shufflevector(__ugtw, __ugtw, 3, 0, 1, 2) & __eqw;
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__sgtw |= (vector signed int)__ugtw;
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return (vector bool long long)__builtin_shufflevector(__sgtw, __sgtw, 1, 1, 3,
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3);
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#else
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__ugtw = __builtin_shufflevector(__ugtw, __ugtw, 1, 2, 3, 0) & __eqw;
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__sgtw |= (vector signed int)__ugtw;
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return (vector bool long long)__builtin_shufflevector(__sgtw, __sgtw, 0, 0, 2,
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2);
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#endif
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}
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpgt(vector unsigned long long __a, vector unsigned long long __b) {
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vector unsigned int __ugtw =
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vec_cmpgt((vector unsigned int)__a, (vector unsigned int)__b);
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vector bool int __eqw =
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vec_cmpeq((vector signed int)__a, (vector signed int)__b);
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#ifdef __LITTLE_ENDIAN__
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__eqw = __builtin_shufflevector(__ugtw, __ugtw, 3, 0, 1, 2) & __eqw;
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__ugtw |= __eqw;
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return (vector bool long long)__builtin_shufflevector(__ugtw, __ugtw, 1, 1, 3,
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3);
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#else
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__eqw = __builtin_shufflevector(__ugtw, __ugtw, 1, 2, 3, 0) & __eqw;
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__ugtw |= __eqw;
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return (vector bool long long)__builtin_shufflevector(__ugtw, __ugtw, 0, 0, 2,
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2);
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#endif
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}
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#endif
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static __inline__ vector bool int __ATTRS_o_ai vec_cmpgt(vector float __a,
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@ -2150,7 +2252,6 @@ vec_cmpge(vector double __a, vector double __b) {
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}
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#endif
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#ifdef __POWER8_VECTOR__
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpge(vector signed long long __a, vector signed long long __b) {
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return ~(vec_cmpgt(__b, __a));
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@ -2160,7 +2261,6 @@ static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmpge(vector unsigned long long __a, vector unsigned long long __b) {
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return ~(vec_cmpgt(__b, __a));
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}
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#endif
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#if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
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static __inline__ vector bool __int128 __ATTRS_o_ai
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@ -2274,7 +2374,6 @@ vec_cmple(vector double __a, vector double __b) {
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}
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#endif
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#ifdef __POWER8_VECTOR__
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmple(vector signed long long __a, vector signed long long __b) {
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return vec_cmpge(__b, __a);
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@ -2284,7 +2383,6 @@ static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmple(vector unsigned long long __a, vector unsigned long long __b) {
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return vec_cmpge(__b, __a);
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}
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#endif
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#if defined(__POWER10_VECTOR__) && defined(__SIZEOF_INT128__)
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static __inline__ vector bool __int128 __ATTRS_o_ai
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@ -2354,7 +2452,6 @@ vec_cmplt(vector unsigned __int128 __a, vector unsigned __int128 __b) {
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}
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#endif
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#ifdef __POWER8_VECTOR__
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static __inline__ vector bool long long __ATTRS_o_ai
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vec_cmplt(vector signed long long __a, vector signed long long __b) {
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return vec_cmpgt(__b, __a);
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@ -2365,6 +2462,7 @@ vec_cmplt(vector unsigned long long __a, vector unsigned long long __b) {
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return vec_cmpgt(__b, __a);
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}
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#ifdef __POWER8_VECTOR__
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/* vec_popcnt */
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static __inline__ vector signed char __ATTRS_o_ai
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@ -8725,6 +8823,46 @@ vec_sl(vector unsigned long long __a, vector unsigned long long __b) {
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__CHAR_BIT__));
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}
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static __inline__ vector long long __ATTRS_o_ai
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vec_sl(vector long long __a, vector unsigned long long __b) {
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return (vector long long)vec_sl((vector unsigned long long)__a, __b);
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}
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#else
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static __inline__ vector unsigned char __ATTRS_o_ai
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vec_vspltb(vector unsigned char __a, unsigned char __b);
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static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_sl(vector unsigned long long __a, vector unsigned long long __b) {
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__b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);
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// Big endian element one (the right doubleword) can be left shifted as-is.
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// The other element needs to be swapped into the right doubleword and
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// shifted. Then the right doublewords of the two result vectors are merged.
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vector signed long long __rightelt =
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(vector signed long long)__builtin_altivec_vslo((vector signed int)__a,
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(vector signed int)__b);
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#ifdef __LITTLE_ENDIAN__
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__rightelt = (vector signed long long)__builtin_altivec_vsl(
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(vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 0));
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#else
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__rightelt = (vector signed long long)__builtin_altivec_vsl(
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(vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 15));
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#endif
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__a = __builtin_shufflevector(__a, __a, 1, 0);
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__b = __builtin_shufflevector(__b, __b, 1, 0);
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vector signed long long __leftelt =
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(vector signed long long)__builtin_altivec_vslo((vector signed int)__a,
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(vector signed int)__b);
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#ifdef __LITTLE_ENDIAN__
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__leftelt = (vector signed long long)__builtin_altivec_vsl(
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(vector signed int)__leftelt, vec_vspltb((vector unsigned char)__b, 0));
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return __builtin_shufflevector(__rightelt, __leftelt, 0, 2);
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#else
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__leftelt = (vector signed long long)__builtin_altivec_vsl(
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(vector signed int)__leftelt, vec_vspltb((vector unsigned char)__b, 15));
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return __builtin_shufflevector(__leftelt, __rightelt, 1, 3);
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#endif
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}
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static __inline__ vector long long __ATTRS_o_ai
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vec_sl(vector long long __a, vector unsigned long long __b) {
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return (vector long long)vec_sl((vector unsigned long long)__a, __b);
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@ -10190,6 +10328,47 @@ vec_sr(vector unsigned long long __a, vector unsigned long long __b) {
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__CHAR_BIT__));
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}
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static __inline__ vector long long __ATTRS_o_ai
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vec_sr(vector long long __a, vector unsigned long long __b) {
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return (vector long long)vec_sr((vector unsigned long long)__a, __b);
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}
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#else
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static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_sr(vector unsigned long long __a, vector unsigned long long __b) {
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__b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);
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// Big endian element zero (the left doubleword) can be right shifted as-is.
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// However the shift amount must be in the right doubleword.
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// The other element needs to be swapped into the left doubleword and
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// shifted. Then the left doublewords of the two result vectors are merged.
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vector signed long long __swapshift = __builtin_shufflevector(__b, __b, 1, 0);
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vector signed long long __leftelt =
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(vector signed long long)__builtin_altivec_vsro((vector signed int)__a,
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__swapshift);
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#ifdef __LITTLE_ENDIAN__
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__leftelt = (vector signed long long)__builtin_altivec_vsr(
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(vector signed int)__leftelt,
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vec_vspltb((vector unsigned char)__swapshift, 0));
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#else
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__leftelt = (vector signed long long)__builtin_altivec_vsr(
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(vector signed int)__leftelt,
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vec_vspltb((vector unsigned char)__swapshift, 15));
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#endif
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__a = __builtin_shufflevector(__a, __a, 1, 0);
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vector signed long long __rightelt =
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(vector signed long long)__builtin_altivec_vsro((vector signed int)__a,
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(vector signed int)__b);
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#ifdef __LITTLE_ENDIAN__
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__rightelt = (vector signed long long)__builtin_altivec_vsr(
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(vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 0));
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return __builtin_shufflevector(__rightelt, __leftelt, 1, 3);
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#else
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__rightelt = (vector signed long long)__builtin_altivec_vsr(
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(vector signed int)__rightelt, vec_vspltb((vector unsigned char)__b, 15));
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return __builtin_shufflevector(__leftelt, __rightelt, 0, 2);
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#endif
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}
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static __inline__ vector long long __ATTRS_o_ai
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vec_sr(vector long long __a, vector unsigned long long __b) {
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return (vector long long)vec_sr((vector unsigned long long)__a, __b);
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@ -10280,6 +10459,18 @@ static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_sra(vector unsigned long long __a, vector unsigned long long __b) {
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return (vector unsigned long long)((vector signed long long)__a >> __b);
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}
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#else
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static __inline__ vector signed long long __ATTRS_o_ai
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vec_sra(vector signed long long __a, vector unsigned long long __b) {
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__b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);
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return __a >> __b;
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}
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static __inline__ vector unsigned long long __ATTRS_o_ai
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vec_sra(vector unsigned long long __a, vector unsigned long long __b) {
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__b %= (vector unsigned long long)(sizeof(unsigned long long) * __CHAR_BIT__);
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return (vector unsigned long long)((vector signed long long)__a >> __b);
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}
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#endif
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/* vec_vsrab */
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@ -2313,3 +2313,282 @@ vector double test_rsqrtd(vector double a, vector double b) {
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// CHECK-LE: fdiv fast <2 x double> <double 1.000000e+00, double 1.000000e+00>
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return vec_rsqrt(a);
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}
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void test_p8overloads_backwards_compat() {
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// CHECK-LABEL: test_p8overloads_backwards_compat
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res_vsll = vec_add(vsll, vsll);
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// CHECK: add <4 x i32>
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// CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw
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// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
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// CHECK: add <4 x i32>
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// CHECK-LE: add <4 x i32>
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// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vaddcuw
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// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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// CHECK-LE: add <4 x i32>
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res_vull = vec_add(vull, vull);
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// CHECK: add <4 x i32>
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// CHECK: call <4 x i32> @llvm.ppc.altivec.vaddcuw
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// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
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// CHECK: add <4 x i32>
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// CHECK-LE: add <4 x i32>
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// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vaddcuw
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// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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// CHECK-LE: add <4 x i32>
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dummy();
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// CHECK: call void @dummy()
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// CHECK-LE: call void @dummy()
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res_vbll = vec_cmpeq(vsll, vsll);
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// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
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// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
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// CHECK: and <4 x i32>
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// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
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// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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// CHECK-LE: and <4 x i32>
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// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
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res_vbll = vec_cmpeq(vull, vull);
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// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
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// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
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// CHECK: and <4 x i32>
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// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
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// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
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// CHECK-LE: and <4 x i32>
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// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
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res_vbll = vec_cmpeq(vbll, vbll);
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// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
dummy();
|
||||
// CHECK: call void @dummy()
|
||||
// CHECK-LE: call void @dummy()
|
||||
|
||||
res_vbll = vec_cmpgt(vsll, vsll);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
res_vbll = vec_cmpgt(vull, vull);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
dummy();
|
||||
// CHECK: call void @dummy()
|
||||
// CHECK-LE: call void @dummy()
|
||||
|
||||
res_vbll = vec_cmpge(vsll, vsll);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
// CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
res_vbll = vec_cmpge(vull, vull);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
// CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
dummy();
|
||||
// CHECK: call void @dummy()
|
||||
// CHECK-LE: call void @dummy()
|
||||
|
||||
res_vbll = vec_cmplt(vsll, vsll);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
res_vbll = vec_cmplt(vull, vull);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
dummy();
|
||||
// CHECK: call void @dummy()
|
||||
// CHECK-LE: call void @dummy()
|
||||
|
||||
res_vbll = vec_cmple(vsll, vsll);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtsw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
// CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
res_vbll = vec_cmple(vull, vull);
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
|
||||
// CHECK: and <4 x i32>
|
||||
// CHECK: or <4 x i32>
|
||||
// CHECK: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
|
||||
// CHECK: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpgtuw
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vcmpequw
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 3, i32 0, i32 1, i32 2>
|
||||
// CHECK-LE: and <4 x i32>
|
||||
// CHECK-LE: or <4 x i32>
|
||||
// CHECK-LE: shufflevector <4 x i32> {{%.*}}, <4 x i32> {{%.*}}, <4 x i32> <i32 1, i32 1, i32 3, i32 3>
|
||||
// CHECK-LE: xor <2 x i64> {{%.*}}, <i64 -1, i64 -1>
|
||||
dummy();
|
||||
// CHECK: call void @dummy()
|
||||
// CHECK-LE: call void @dummy()
|
||||
|
||||
res_vsll = vec_sl(vsll, vull);
|
||||
// CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>
|
||||
// CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>
|
||||
res_vull = vec_sl(vull, vull);
|
||||
// CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>
|
||||
// CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vslo
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsl
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>
|
||||
dummy();
|
||||
// CHECK: call void @dummy()
|
||||
// CHECK-LE: call void @dummy()
|
||||
|
||||
res_vsll = vec_sr(vsll, vull);
|
||||
// CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>
|
||||
// CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>
|
||||
res_vull = vec_sr(vull, vull);
|
||||
// CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 0, i32 2>
|
||||
// CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 0>
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsro
|
||||
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vsr
|
||||
// CHECK-LE: shufflevector <2 x i64> {{%.*}}, <2 x i64> {{%.*}}, <2 x i32> <i32 1, i32 3>
|
||||
dummy();
|
||||
// CHECK: call void @dummy()
|
||||
// CHECK-LE: call void @dummy()
|
||||
|
||||
res_vsll = vec_sra(vsll, vull);
|
||||
// CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK: ashr <2 x i64>
|
||||
// CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK-LE: ashr <2 x i64>
|
||||
res_vull = vec_sra(vull, vull);
|
||||
// CHECK: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK: ashr <2 x i64>
|
||||
// CHECK-LE: urem <2 x i64> {{%.*}}, <i64 64, i64 64>
|
||||
// CHECK-LE: ashr <2 x i64>
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue