forked from OSchip/llvm-project
GlobalISel: Implement widenScalar for G_SITOFP/G_UITOFP sources
Legalize 16-bit G_SITOFP/G_UITOFP for AMDGPU. llvm-svn: 373287
This commit is contained in:
Matt Arsenault
parent
77ac400117
commit
ed85b0cee6
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@ -1622,13 +1622,15 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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case TargetOpcode::G_FPTOSI:
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case TargetOpcode::G_FPTOUI:
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if (TypeIdx != 0)
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return UnableToLegalize;
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Observer.changingInstr(MI);
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widenScalarDst(MI, WideTy);
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if (TypeIdx == 0)
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widenScalarDst(MI, WideTy);
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else
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widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
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Observer.changedInstr(MI);
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return Legalized;
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case TargetOpcode::G_SITOFP:
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if (TypeIdx != 1)
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return UnableToLegalize;
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@ -423,9 +423,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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.customFor({{S64, S64}})
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.scalarize(0);
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getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalFor({{S32, S32}, {S32, S64}, {S32, S16}})
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.scalarize(0);
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auto &FPToI = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
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.legalFor({{S32, S32}, {S32, S64}, {S32, S16}});
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if (ST.has16BitInsts())
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FPToI.legalFor({{S16, S16}});
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else
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FPToI.minScalar(1, S32);
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FPToI.minScalar(0, S32)
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.scalarize(0);
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getActionDefinitionsBuilder(G_INTRINSIC_ROUND)
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.legalFor({S32, S64})
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@ -1,8 +1,8 @@
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;RUN: llc -mtriple=aarch64-unknown-unknown -o - -global-isel -global-isel-abort=2 %s 2>&1 | FileCheck %s
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; CHECK: fallback
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; CHECK-LABEL: foo
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define i16 @foo(half* %p) {
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%tmp0 = load half, half* %p
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%tmp1 = fptoui half %tmp0 to i16
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define i16 @foo(fp128* %p) {
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%tmp0 = load fp128, fp128* %p
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%tmp1 = fptoui fp128 %tmp0 to i16
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ret i16 %tmp1
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}
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@ -1,5 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
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---
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name: test_fptosi_s32_to_s32
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@ -7,10 +8,14 @@ body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fptosi_s32_to_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; CHECK: $vgpr0 = COPY [[FPTOSI]](s32)
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; SI-LABEL: name: test_fptosi_s32_to_s32
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; SI: $vgpr0 = COPY [[FPTOSI]](s32)
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; VI-LABEL: name: test_fptosi_s32_to_s32
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; VI: $vgpr0 = COPY [[FPTOSI]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_FPTOSI %0
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$vgpr0 = COPY %1
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@ -22,10 +27,14 @@ body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_fptosi_s64_to_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
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; CHECK: $vgpr0 = COPY [[FPTOSI]](s32)
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; SI-LABEL: name: test_fptosi_s64_to_s32
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; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
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; SI: $vgpr0 = COPY [[FPTOSI]](s32)
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; VI-LABEL: name: test_fptosi_s64_to_s32
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; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
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; VI: $vgpr0 = COPY [[FPTOSI]](s32)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_FPTOSI %0
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$vgpr0 = COPY %1
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@ -37,13 +46,20 @@ body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_fptosi_v2s32_to_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s32)
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; CHECK: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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; SI-LABEL: name: test_fptosi_v2s32_to_v2s32
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; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s32)
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; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s32)
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; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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; VI-LABEL: name: test_fptosi_v2s32_to_v2s32
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; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s32)
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; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s32)
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; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
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; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(<2 x s32>) = G_FPTOSI %0
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$vgpr0_vgpr1 = COPY %1
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@ -55,14 +71,91 @@ body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: test_fptosi_v2s64_to_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; CHECK: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s64)
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; CHECK: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s64)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
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; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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; SI-LABEL: name: test_fptosi_v2s64_to_v2s32
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; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s64)
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; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s64)
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; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
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; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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; VI-LABEL: name: test_fptosi_v2s64_to_v2s32
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; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[UV]](s64)
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; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[UV1]](s64)
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; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOSI]](s32), [[FPTOSI1]](s32)
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; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
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%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(<2 x s32>) = G_FPTOSI %0
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$vgpr0_vgpr1 = COPY %1
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...
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---
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name: test_fptosi_s16_to_s16
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_fptosi_s16_to_s16
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
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; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; SI: $vgpr0 = COPY [[COPY1]](s32)
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; VI-LABEL: name: test_fptosi_s16_to_s16
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
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; VI: [[FPTOSI:%[0-9]+]]:_(s16) = G_FPTOSI [[TRUNC]](s16)
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; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTOSI]](s16)
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; VI: $vgpr0 = COPY [[ANYEXT]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_TRUNC %0
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%2:_(s16) = G_FPTOSI %1
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%3:_(s32) = G_ANYEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: test_fptosi_s32_to_s16
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_fptosi_s32_to_s16
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; SI: $vgpr0 = COPY [[COPY1]](s32)
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; VI-LABEL: name: test_fptosi_s32_to_s16
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s32)
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; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; VI: $vgpr0 = COPY [[COPY1]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s16) = G_FPTOSI %0
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%2:_(s32) = G_ANYEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: test_fptosi_s64_to_s16
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; SI-LABEL: name: test_fptosi_s64_to_s16
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; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
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; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; SI: $vgpr0 = COPY [[COPY1]](s32)
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; VI-LABEL: name: test_fptosi_s64_to_s16
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; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[COPY]](s64)
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; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOSI]](s32)
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; VI: $vgpr0 = COPY [[COPY1]](s32)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s16) = G_FPTOSI %0
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%2:_(s32) = G_ANYEXT %1
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$vgpr0 = COPY %2
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...
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@ -1,5 +1,6 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
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---
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name: test_fptoui_s32_s32
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: test_fptoui_s32_s32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
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; CHECK: $vgpr0 = COPY [[FPTOUI]](s32)
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; SI-LABEL: name: test_fptoui_s32_s32
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
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; SI: $vgpr0 = COPY [[FPTOUI]](s32)
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; VI-LABEL: name: test_fptoui_s32_s32
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
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; VI: $vgpr0 = COPY [[FPTOUI]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_FPTOUI %0
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$vgpr0 = COPY %1
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_fptoui_s32_s64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
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; CHECK: $vgpr0 = COPY [[FPTOUI]](s32)
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; SI-LABEL: name: test_fptoui_s32_s64
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; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
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; SI: $vgpr0 = COPY [[FPTOUI]](s32)
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; VI-LABEL: name: test_fptoui_s32_s64
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; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
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; VI: $vgpr0 = COPY [[FPTOUI]](s32)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_FPTOUI %0
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$vgpr0 = COPY %1
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_fptoui_v2s32_to_v2s32
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; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
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; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](s32)
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; CHECK: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](s32)
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
|
||||
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
; SI-LABEL: name: test_fptoui_v2s32_to_v2s32
|
||||
; SI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
|
||||
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](s32)
|
||||
; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](s32)
|
||||
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
|
||||
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
; VI-LABEL: name: test_fptoui_v2s32_to_v2s32
|
||||
; VI: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
; VI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
|
||||
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](s32)
|
||||
; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](s32)
|
||||
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
|
||||
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
|
||||
%1:_(<2 x s32>) = G_FPTOUI %0
|
||||
$vgpr0_vgpr1 = COPY %1
|
||||
|
|
@ -55,14 +71,91 @@ body: |
|
|||
bb.0:
|
||||
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
|
||||
; CHECK-LABEL: name: test_fptoui_v2s64_to_v2s32
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; CHECK: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
|
||||
; CHECK: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](s64)
|
||||
; CHECK: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](s64)
|
||||
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
|
||||
; CHECK: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
; SI-LABEL: name: test_fptoui_v2s64_to_v2s32
|
||||
; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
|
||||
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](s64)
|
||||
; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](s64)
|
||||
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
|
||||
; SI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
; VI-LABEL: name: test_fptoui_v2s64_to_v2s32
|
||||
; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
|
||||
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[UV]](s64)
|
||||
; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[UV1]](s64)
|
||||
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[FPTOUI]](s32), [[FPTOUI1]](s32)
|
||||
; VI: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
|
||||
%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
|
||||
%1:_(<2 x s32>) = G_FPTOUI %0
|
||||
$vgpr0_vgpr1 = COPY %1
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fptoui_s16_to_s16
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
|
||||
; SI-LABEL: name: test_fptoui_s16_to_s16
|
||||
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
|
||||
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FPEXT]](s32)
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
|
||||
; SI: $vgpr0 = COPY [[COPY1]](s32)
|
||||
; VI-LABEL: name: test_fptoui_s16_to_s16
|
||||
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
|
||||
; VI: [[FPTOUI:%[0-9]+]]:_(s16) = G_FPTOUI [[TRUNC]](s16)
|
||||
; VI: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTOUI]](s16)
|
||||
; VI: $vgpr0 = COPY [[ANYEXT]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s16) = G_TRUNC %0
|
||||
%2:_(s16) = G_FPTOUI %1
|
||||
%3:_(s32) = G_ANYEXT %2
|
||||
$vgpr0 = COPY %3
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fptoui_s32_to_s16
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0
|
||||
|
||||
; SI-LABEL: name: test_fptoui_s32_to_s16
|
||||
; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
|
||||
; SI: $vgpr0 = COPY [[COPY1]](s32)
|
||||
; VI-LABEL: name: test_fptoui_s32_to_s16
|
||||
; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s32)
|
||||
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
|
||||
; VI: $vgpr0 = COPY [[COPY1]](s32)
|
||||
%0:_(s32) = COPY $vgpr0
|
||||
%1:_(s16) = G_FPTOUI %0
|
||||
%2:_(s32) = G_ANYEXT %1
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
|
||||
---
|
||||
name: test_fptoui_s64_to_s16
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1
|
||||
|
||||
; SI-LABEL: name: test_fptoui_s64_to_s16
|
||||
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
|
||||
; SI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
|
||||
; SI: $vgpr0 = COPY [[COPY1]](s32)
|
||||
; VI-LABEL: name: test_fptoui_s64_to_s16
|
||||
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
|
||||
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[COPY]](s64)
|
||||
; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[FPTOUI]](s32)
|
||||
; VI: $vgpr0 = COPY [[COPY1]](s32)
|
||||
%0:_(s64) = COPY $vgpr0_vgpr1
|
||||
%1:_(s16) = G_FPTOUI %0
|
||||
%2:_(s32) = G_ANYEXT %1
|
||||
$vgpr0 = COPY %2
|
||||
...
|
||||
|
|
|
|||
Loading…
Reference in New Issue