forked from OSchip/llvm-project
[AArch64][SVE] Add patterns for some integer vector instructions
Add pattern matching for SVE vector instructions: -- add, sub, and, or, xor instructions -- sqadd, uqadd, sqsub, uqsub target-independent intrinsics -- bic intrinsics -- predicated add, sub, subr intrinsics Patch Review: https://reviews.llvm.org/D69128 Patch authored by: dancgr (Danilo Carvalho Grael)
This commit is contained in:
Ehsan Amiri
amehsan
parent
2dad729f0c
commit
ed7bcb2cb1
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@ -815,10 +815,23 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
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class AdvSIMD_Pred2VectorArg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty],
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[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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//
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// Integer arithmetic
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//
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def int_aarch64_sve_add : AdvSIMD_Pred2VectorArg_Intrinsic;
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def int_aarch64_sve_sub : AdvSIMD_Pred2VectorArg_Intrinsic;
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def int_aarch64_sve_subr : AdvSIMD_Pred2VectorArg_Intrinsic;
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def int_aarch64_sve_bic : AdvSIMD_2VectorArg_Intrinsic;
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def int_aarch64_sve_abs : AdvSIMD_Merged1VectorArg_Intrinsic;
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def int_aarch64_sve_neg : AdvSIMD_Merged1VectorArg_Intrinsic;
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@ -183,6 +183,13 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
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addRegisterClass(MVT::nxv4f32, &AArch64::ZPRRegClass);
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addRegisterClass(MVT::nxv1f64, &AArch64::ZPRRegClass);
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addRegisterClass(MVT::nxv2f64, &AArch64::ZPRRegClass);
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for (auto VT : { MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64 }) {
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setOperationAction(ISD::SADDSAT, VT, Legal);
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setOperationAction(ISD::UADDSAT, VT, Legal);
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setOperationAction(ISD::SSUBSAT, VT, Legal);
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setOperationAction(ISD::USUBSAT, VT, Legal);
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}
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}
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// Compute derived properties from the register classes
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@ -18,26 +18,26 @@ let Predicates = [HasSVE] in {
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def SETFFR : sve_int_setffr<"setffr">;
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def WRFFR : sve_int_wrffr<"wrffr">;
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defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add">;
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defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub">;
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defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd">;
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defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd">;
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defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub">;
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defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub">;
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defm ADD_ZZZ : sve_int_bin_cons_arit_0<0b000, "add", add>;
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defm SUB_ZZZ : sve_int_bin_cons_arit_0<0b001, "sub", sub>;
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defm SQADD_ZZZ : sve_int_bin_cons_arit_0<0b100, "sqadd", saddsat>;
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defm UQADD_ZZZ : sve_int_bin_cons_arit_0<0b101, "uqadd", uaddsat>;
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defm SQSUB_ZZZ : sve_int_bin_cons_arit_0<0b110, "sqsub", ssubsat>;
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defm UQSUB_ZZZ : sve_int_bin_cons_arit_0<0b111, "uqsub", usubsat>;
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defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and">;
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defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr">;
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defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor">;
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defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic">;
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defm AND_ZZZ : sve_int_bin_cons_log<0b00, "and", and>;
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defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr", or>;
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defm EOR_ZZZ : sve_int_bin_cons_log<0b10, "eor", xor>;
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defm BIC_ZZZ : sve_int_bin_cons_log<0b11, "bic", int_aarch64_sve_bic>;
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defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add">;
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defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub">;
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defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr">;
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defm ADD_ZPmZ : sve_int_bin_pred_arit_0<0b000, "add", int_aarch64_sve_add>;
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defm SUB_ZPmZ : sve_int_bin_pred_arit_0<0b001, "sub", int_aarch64_sve_sub>;
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defm SUBR_ZPmZ : sve_int_bin_pred_arit_0<0b011, "subr", int_aarch64_sve_subr>;
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defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr">;
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defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor">;
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defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">;
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defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic">;
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defm ORR_ZPmZ : sve_int_bin_pred_log<0b000, "orr", null_frag>;
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defm EOR_ZPmZ : sve_int_bin_pred_log<0b001, "eor", null_frag>;
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defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and", null_frag>;
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defm BIC_ZPmZ : sve_int_bin_pred_log<0b011, "bic", null_frag>;
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defm ADD_ZI : sve_int_arith_imm0<0b000, "add">;
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defm SUB_ZI : sve_int_arith_imm0<0b001, "sub">;
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@ -73,14 +73,14 @@ let Predicates = [HasSVE] in {
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defm UMIN_ZI : sve_int_arith_imm1<0b11, "umin", imm0_255>;
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defm MUL_ZI : sve_int_arith_imm2<"mul">;
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defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul">;
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defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh">;
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defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh">;
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defm MUL_ZPmZ : sve_int_bin_pred_arit_2<0b000, "mul", null_frag>;
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defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh", null_frag>;
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defm UMULH_ZPmZ : sve_int_bin_pred_arit_2<0b011, "umulh", null_frag>;
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defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv">;
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defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv">;
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defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr">;
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defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr">;
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defm SDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b100, "sdiv", null_frag>;
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defm UDIV_ZPmZ : sve_int_bin_pred_arit_2_div<0b101, "udiv", null_frag>;
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defm SDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b110, "sdivr", null_frag>;
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defm UDIVR_ZPmZ : sve_int_bin_pred_arit_2_div<0b111, "udivr", null_frag>;
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defm SDOT_ZZZ : sve_intx_dot<0b0, "sdot", int_aarch64_sve_sdot>;
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defm UDOT_ZZZ : sve_intx_dot<0b1, "udot", int_aarch64_sve_udot>;
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@ -105,12 +105,12 @@ let Predicates = [HasSVE] in {
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defm FABS_ZPmZ : sve_int_un_pred_arit_1_fp<0b100, "fabs">;
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defm FNEG_ZPmZ : sve_int_un_pred_arit_1_fp<0b101, "fneg">;
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defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax">;
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defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax">;
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defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">;
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defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin">;
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defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd">;
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defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd">;
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defm SMAX_ZPmZ : sve_int_bin_pred_arit_1<0b000, "smax", null_frag>;
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defm UMAX_ZPmZ : sve_int_bin_pred_arit_1<0b001, "umax", null_frag>;
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defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin", null_frag>;
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defm UMIN_ZPmZ : sve_int_bin_pred_arit_1<0b011, "umin", null_frag>;
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defm SABD_ZPmZ : sve_int_bin_pred_arit_1<0b100, "sabd", null_frag>;
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defm UABD_ZPmZ : sve_int_bin_pred_arit_1<0b101, "uabd", null_frag>;
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defm FRECPE_ZZ : sve_fp_2op_u_zd<0b110, "frecpe">;
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defm FRSQRTE_ZZ : sve_fp_2op_u_zd<0b111, "frsqrte">;
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@ -288,6 +288,11 @@ class SVE_1_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
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: Pat<(vtd (op vt1:$Op1)),
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(inst $Op1)>;
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class SVE_2_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
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ValueType vt2, Instruction inst>
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: Pat<(vtd (op vt1:$Op1, vt2:$Op2)),
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(inst $Op1, $Op2)>;
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class SVE_3_Op_Pat<ValueType vtd, SDPatternOperator op, ValueType vt1,
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ValueType vt2, ValueType vt3, Instruction inst>
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: Pat<(vtd (op vt1:$Op1, vt2:$Op2, vt3:$Op3)),
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@ -1122,11 +1127,16 @@ class sve_int_bin_cons_arit_0<bits<2> sz8_64, bits<3> opc, string asm,
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm> {
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multiclass sve_int_bin_cons_arit_0<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_bin_cons_arit_0<0b00, opc, asm, ZPR8>;
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def _H : sve_int_bin_cons_arit_0<0b01, opc, asm, ZPR16>;
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def _S : sve_int_bin_cons_arit_0<0b10, opc, asm, ZPR32>;
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def _D : sve_int_bin_cons_arit_0<0b11, opc, asm, ZPR64>;
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def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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//===----------------------------------------------------------------------===//
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@ -1801,38 +1811,61 @@ class sve_int_bin_pred_arit_log<bits<2> sz8_64, bits<2> fmt, bits<3> opc,
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let ElementSize = zprty.ElementSize;
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}
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multiclass sve_int_bin_pred_log<bits<3> opc, string asm> {
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multiclass sve_int_bin_pred_log<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b11, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b11, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b11, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b11, opc, asm, ZPR64>;
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def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm> {
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multiclass sve_int_bin_pred_arit_0<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b00, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b00, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b00, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b00, opc, asm, ZPR64>;
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def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm> {
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multiclass sve_int_bin_pred_arit_1<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b01, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b01, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b01, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b01, opc, asm, ZPR64>;
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def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm> {
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multiclass sve_int_bin_pred_arit_2<bits<3> opc, string asm, SDPatternOperator op> {
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def _B : sve_int_bin_pred_arit_log<0b00, 0b10, opc, asm, ZPR8>;
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def _H : sve_int_bin_pred_arit_log<0b01, 0b10, opc, asm, ZPR16>;
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def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
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def : SVE_3_Op_Pat<nxv16i8, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
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def : SVE_3_Op_Pat<nxv8i16, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
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def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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// Special case for divides which are not defined for 8b/16b elements.
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multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm> {
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multiclass sve_int_bin_pred_arit_2_div<bits<3> opc, string asm, SDPatternOperator op> {
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def _S : sve_int_bin_pred_arit_log<0b10, 0b10, opc, asm, ZPR32>;
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def _D : sve_int_bin_pred_arit_log<0b11, 0b10, opc, asm, ZPR64>;
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def : SVE_3_Op_Pat<nxv4i32, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
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def : SVE_3_Op_Pat<nxv2i64, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
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}
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//===----------------------------------------------------------------------===//
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@ -3086,9 +3119,14 @@ class sve_int_bin_cons_log<bits<2> opc, string asm>
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let Inst{4-0} = Zd;
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}
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multiclass sve_int_bin_cons_log<bits<2> opc, string asm> {
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multiclass sve_int_bin_cons_log<bits<2> opc, string asm, SDPatternOperator op> {
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def NAME : sve_int_bin_cons_log<opc, asm>;
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def : SVE_2_Op_Pat<nxv16i8, op, nxv16i8, nxv16i8, !cast<Instruction>(NAME)>;
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def : SVE_2_Op_Pat<nxv8i16, op, nxv8i16, nxv8i16, !cast<Instruction>(NAME)>;
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def : SVE_2_Op_Pat<nxv4i32, op, nxv4i32, nxv4i32, !cast<Instruction>(NAME)>;
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def : SVE_2_Op_Pat<nxv2i64, op, nxv2i64, nxv2i64, !cast<Instruction>(NAME)>;
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def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
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(!cast<Instruction>(NAME) ZPR8:$Zd, ZPR8:$Zn, ZPR8:$Zm), 1>;
|
||||
def : InstAlias<asm # "\t$Zd, $Zn, $Zm",
|
||||
|
|
|
|||
|
|
@ -0,0 +1,143 @@
|
|||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
|
||||
|
||||
define <vscale x 16 x i8> @add_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: add_i8:
|
||||
; CHECK: add z0.b, p0/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a,
|
||||
<vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @add_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: add_i16:
|
||||
; CHECK: add z0.h, p0/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a,
|
||||
<vscale x 8 x i16> %b)
|
||||
ret <vscale x 8 x i16> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @add_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: add_i32:
|
||||
; CHECK: add z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a,
|
||||
<vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @add_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: add_i64:
|
||||
; CHECK: add z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a,
|
||||
<vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %out
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: sub_i8:
|
||||
; CHECK: sub z0.b, p0/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a,
|
||||
<vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: sub_i16:
|
||||
; CHECK: sub z0.h, p0/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a,
|
||||
<vscale x 8 x i16> %b)
|
||||
ret <vscale x 8 x i16> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: sub_i32:
|
||||
; CHECK: sub z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a,
|
||||
<vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: sub_i64:
|
||||
; CHECK: sub z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a,
|
||||
<vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %out
|
||||
}
|
||||
|
||||
|
||||
|
||||
define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: subr_i8:
|
||||
; CHECK: subr z0.b, p0/m, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %pg,
|
||||
<vscale x 16 x i8> %a,
|
||||
<vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %out
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: subr_i16:
|
||||
; CHECK: subr z0.h, p0/m, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg,
|
||||
<vscale x 8 x i16> %a,
|
||||
<vscale x 8 x i16> %b)
|
||||
ret <vscale x 8 x i16> %out
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: subr_i32:
|
||||
; CHECK: subr z0.s, p0/m, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg,
|
||||
<vscale x 4 x i32> %a,
|
||||
<vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %out
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: subr_i64:
|
||||
; CHECK: subr z0.d, p0/m, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg,
|
||||
<vscale x 2 x i64> %a,
|
||||
<vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %out
|
||||
}
|
||||
|
||||
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.aarch64.sve.add.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.add.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.add.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
|
||||
|
||||
define <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: add_i64
|
||||
; CHECK: add z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = add <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: add_i32
|
||||
; CHECK: add z0.s, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = add <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: add_i16
|
||||
; CHECK: add z0.h, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = add <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: add_i8
|
||||
; CHECK: add z0.b, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = add <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: sub_i64
|
||||
; CHECK: sub z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = sub <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: sub_i32
|
||||
; CHECK: sub z0.s, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = sub <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: sub_i16
|
||||
; CHECK: sub z0.h, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = sub <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: sub_i8
|
||||
; CHECK: sub z0.b, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = sub <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @sqadd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: sqadd_i64
|
||||
; CHECK: sqadd z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqadd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: sqadd_i32
|
||||
; CHECK: sqadd z0.s, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @sqadd_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: sqadd_i16
|
||||
; CHECK: sqadd z0.h, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @sqadd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: sqadd_i8
|
||||
; CHECK: sqadd z0.b, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
|
||||
define <vscale x 2 x i64> @sqsub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: sqsub_i64
|
||||
; CHECK: sqsub z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @sqsub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: sqsub_i32
|
||||
; CHECK: sqsub z0.s, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @sqsub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: sqsub_i16
|
||||
; CHECK: sqsub z0.h, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @sqsub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: sqsub_i8
|
||||
; CHECK: sqsub z0.b, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
|
||||
define <vscale x 2 x i64> @uqadd_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: uqadd_i64
|
||||
; CHECK: uqadd z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @uqadd_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: uqadd_i32
|
||||
; CHECK: uqadd z0.s, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @uqadd_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: uqadd_i16
|
||||
; CHECK: uqadd z0.h, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @uqadd_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: uqadd_i8
|
||||
; CHECK: uqadd z0.b, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
|
||||
define <vscale x 2 x i64> @uqsub_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: uqsub_i64
|
||||
; CHECK: uqsub z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @uqsub_i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: uqsub_i32
|
||||
; CHECK: uqsub z0.s, z0.s, z1.s
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @uqsub_i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: uqsub_i16
|
||||
; CHECK: uqsub z0.h, z0.h, z1.h
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @uqsub_i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: uqsub_i8
|
||||
; CHECK: uqsub z0.b, z0.b, z1.b
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
|
||||
declare <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
declare <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
|
||||
|
||||
define <vscale x 2 x i64> @and_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: and_d
|
||||
; CHECK: and z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = and <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @and_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: and_s
|
||||
; CHECK: and z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = and <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @and_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: and_h
|
||||
; CHECK: and z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = and <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @and_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: and_b
|
||||
; CHECK: and z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = and <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
define <vscale x 2 x i64> @or_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: or_d
|
||||
; CHECK: orr z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = or <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @or_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: or_s
|
||||
; CHECK: orr z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = or <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @or_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: or_h
|
||||
; CHECK: orr z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = or <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @or_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: or_b
|
||||
; CHECK: orr z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = or <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @xor_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: xor_d
|
||||
; CHECK: eor z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = xor <vscale x 2 x i64> %a, %b
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @xor_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: xor_s
|
||||
; CHECK: eor z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = xor <vscale x 4 x i32> %a, %b
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @xor_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: xor_h
|
||||
; CHECK: eor z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = xor <vscale x 8 x i16> %a, %b
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @xor_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: xor_b
|
||||
; CHECK: eor z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = xor <vscale x 16 x i8> %a, %b
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
define <vscale x 2 x i64> @bic_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
|
||||
; CHECK-LABEL: bic_d
|
||||
; CHECK: bic z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i64> %a,
|
||||
<vscale x 2 x i64> %b)
|
||||
ret <vscale x 2 x i64> %res
|
||||
}
|
||||
|
||||
define <vscale x 4 x i32> @bic_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
|
||||
; CHECK-LABEL: bic_s
|
||||
; CHECK: bic z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i32> %a,
|
||||
<vscale x 4 x i32> %b)
|
||||
ret <vscale x 4 x i32> %res
|
||||
}
|
||||
|
||||
define <vscale x 8 x i16> @bic_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
|
||||
; CHECK-LABEL: bic_h
|
||||
; CHECK: bic z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i16> %a,
|
||||
<vscale x 8 x i16> %b)
|
||||
|
||||
ret <vscale x 8 x i16> %res
|
||||
}
|
||||
|
||||
define <vscale x 16 x i8> @bic_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
|
||||
; CHECK-LABEL: bic_b
|
||||
; CHECK: bic z0.d, z0.d, z1.d
|
||||
; CHECK-NEXT: ret
|
||||
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i8> %a,
|
||||
<vscale x 16 x i8> %b)
|
||||
ret <vscale x 16 x i8> %res
|
||||
}
|
||||
|
||||
declare <vscale x 2 x i64> @llvm.aarch64.sve.bic.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
|
||||
declare <vscale x 4 x i32> @llvm.aarch64.sve.bic.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
||||
declare <vscale x 8 x i16> @llvm.aarch64.sve.bic.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
|
||||
declare <vscale x 16 x i8> @llvm.aarch64.sve.bic.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
|
||||
Loading…
Reference in New Issue