From ed6c0408fa6a23ee3e7f076d561044b602c9decf Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Fri, 13 Jul 2012 20:44:29 +0000 Subject: [PATCH] Remove variable_ops from call instructions in most targets. Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. llvm-svn: 160189 --- llvm/lib/Target/CellSPU/SPUInstrInfo.td | 4 ++-- llvm/lib/Target/Hexagon/HexagonInstrInfo.td | 10 ++++----- llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td | 4 ++-- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td | 6 ++--- llvm/lib/Target/MBlaze/MBlazeInstrInfo.td | 4 ++-- llvm/lib/Target/MSP430/MSP430InstrInfo.td | 6 ++--- llvm/lib/Target/Mips/Mips16InstrInfo.td | 2 +- llvm/lib/Target/Mips/MipsInstrInfo.td | 6 ++--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 22 +++++++++---------- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 18 +++++++-------- llvm/lib/Target/XCore/XCoreInstrInfo.td | 8 +++---- 11 files changed, 44 insertions(+), 46 deletions(-) diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.td b/llvm/lib/Target/CellSPU/SPUInstrInfo.td index f76ebd75bfef..117acd736aaa 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.td +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.td @@ -3421,14 +3421,14 @@ let isCall = 1, // Branch relative and set link: Used if we actually know that the target // is within [-32768, 32767] bytes of the target def BRSL: - BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func, variable_ops), + BranchSetLink<0b011001100, (outs), (ins relcalltarget:$func), "brsl\t$$lr, $func", [(SPUcall (SPUpcrel tglobaladdr:$func, 0))]>; // Branch absolute and set link: Used if we actually know that the target // is an absolute address def BRASL: - BranchSetLink<0b011001100, (outs), (ins calltarget:$func, variable_ops), + BranchSetLink<0b011001100, (outs), (ins calltarget:$func), "brasl\t$$lr, $func", [(SPUcall (SPUaform tglobaladdr:$func, 0))]>; diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td index 16448004a8c6..c7be5cea56e2 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.td @@ -2566,7 +2566,7 @@ let Defs = [R29, R30, R31], Uses = [R29] in { let isCall = 1, neverHasSideEffects = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def CALL : JInst<(outs), (ins calltarget:$dst, variable_ops), + def CALL : JInst<(outs), (ins calltarget:$dst), "call $dst", []>; } @@ -2574,7 +2574,7 @@ let isCall = 1, neverHasSideEffects = 1, let isCall = 1, neverHasSideEffects = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def CALLR : JRInst<(outs), (ins IntRegs:$dst, variable_ops), + def CALLR : JRInst<(outs), (ins IntRegs:$dst), "callr $dst", []>; } @@ -2583,20 +2583,20 @@ let isCall = 1, neverHasSideEffects = 1, let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def TCRETURNtg : JInst<(outs), (ins calltarget:$dst, variable_ops), + def TCRETURNtg : JInst<(outs), (ins calltarget:$dst), "jump $dst // TAILCALL", []>; } let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def TCRETURNtext : JInst<(outs), (ins calltarget:$dst, variable_ops), + def TCRETURNtext : JInst<(outs), (ins calltarget:$dst), "jump $dst // TAILCALL", []>; } let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def TCRETURNR : JInst<(outs), (ins IntRegs:$dst, variable_ops), + def TCRETURNR : JInst<(outs), (ins IntRegs:$dst), "jumpr $dst // TAILCALL", []>; } // Map call instruction. diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td index 2bd6770efd7d..157ab3d0e38c 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV3.td @@ -19,7 +19,7 @@ let isCall = 1, neverHasSideEffects = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def CALLv3 : JInst<(outs), (ins calltarget:$dst, variable_ops), + def CALLv3 : JInst<(outs), (ins calltarget:$dst), "call $dst", []>, Requires<[HasV3T]>; } @@ -35,7 +35,7 @@ let isCall = 1, neverHasSideEffects = 1, let isCall = 1, neverHasSideEffects = 1, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { - def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst, variable_ops), + def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst), "callr $dst", []>, Requires<[HasV3TOnly]>; } diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td index 9878503874cd..70448fc7af38 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td @@ -5156,7 +5156,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, isPredicable = 1, let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, Defs = [R29, R30, R31, PC] in { def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs), - (ins calltarget:$dst, variable_ops), + (ins calltarget:$dst), "jump $dst // Restore_and_dealloc_return", []>, Requires<[HasV4T]>; @@ -5166,7 +5166,7 @@ let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, let isCall = 1, isBarrier = 1, Defs = [R29, R30, R31, PC] in { def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs), - (ins calltarget:$dst, variable_ops), + (ins calltarget:$dst), "call $dst // Restore_and_dealloc_before_tailcall", []>, Requires<[HasV4T]>; @@ -5176,7 +5176,7 @@ let isCall = 1, isBarrier = 1, let isCall = 1, isBarrier = 1, Uses = [R29, R31] in { def SAVE_REGISTERS_CALL_V4 : JInst<(outs), - (ins calltarget:$dst, variable_ops), + (ins calltarget:$dst), "call $dst // Save_calle_saved_registers", []>, Requires<[HasV4T]>; diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td index 02a21574f493..139bf7156a69 100644 --- a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td +++ b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.td @@ -295,7 +295,7 @@ class BranchI op, bits<5> br, string instr_asm> : // Branch and Link Instructions //===----------------------------------------------------------------------===// class BranchL op, bits<5> br, bits<11> flags, string instr_asm> : - TA { let ra = br; @@ -303,7 +303,7 @@ class BranchL op, bits<5> br, bits<11> flags, string instr_asm> : } class BranchLI op, bits<5> br, string instr_asm> : - TB { let ra = br; diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.td b/llvm/lib/Target/MSP430/MSP430InstrInfo.td index 4348dd5e54e6..f003574eda00 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.td +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.td @@ -210,13 +210,13 @@ let isCall = 1 in let Defs = [R12W, R13W, R14W, R15W, SRW], Uses = [SPW] in { def CALLi : II16i<0x0, - (outs), (ins i16imm:$dst, variable_ops), + (outs), (ins i16imm:$dst), "call\t$dst", [(MSP430call imm:$dst)]>; def CALLr : II16r<0x0, - (outs), (ins GR16:$dst, variable_ops), + (outs), (ins GR16:$dst), "call\t$dst", [(MSP430call GR16:$dst)]>; def CALLm : II16m<0x0, - (outs), (ins memsrc:$dst, variable_ops), + (outs), (ins memsrc:$dst), "call\t${dst:mem}", [(MSP430call (load addr:$dst))]>; } diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td index f6b876212526..4fd8dd4e48f4 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td @@ -44,7 +44,7 @@ def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2), // Jump and Link (Call) let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in def JumpLinkReg16: - FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops), + FRR16_JALRC<(outs), (ins CPU16Regs:$rs), "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>; // Small immediates diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td index 973d00bb0129..c47f0cbf4bf0 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -649,7 +649,7 @@ class RetBase: JumpFR { // Jump and Link (Call) let isCall=1, hasDelaySlot=1, Defs = [RA] in { class JumpLink op, string instr_asm>: - FJ { let DecoderMethod = "DecodeJumpTarget"; @@ -657,7 +657,7 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in { class JumpLinkReg op, bits<6> func, string instr_asm, RegisterClass RC>: - FR { let rt = 0; let rd = 31; @@ -665,7 +665,7 @@ let isCall=1, hasDelaySlot=1, Defs = [RA] in { } class BranchLink _rt, RegisterClass RC>: - FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops), + FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { let rt = _rt; } diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index a2bd55f53336..91c5366e5c20 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -68,15 +68,15 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { // Convenient aliases for call instructions let Uses = [RM] in { def BL8_Darwin : IForm<18, 0, 1, - (outs), (ins calltarget:$func, variable_ops), + (outs), (ins calltarget:$func), "bl $func", BrB, []>; // See Pat patterns below. def BLA8_Darwin : IForm<18, 1, 1, - (outs), (ins aaddr:$func, variable_ops), + (outs), (ins aaddr:$func), "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; } let Uses = [CTR8, RM] in { def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, - (outs), (ins variable_ops), + (outs), (ins), "bctrl", BrB, [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; } @@ -88,27 +88,27 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { // Convenient aliases for call instructions let Uses = [RM] in { def BL8_ELF : IForm<18, 0, 1, - (outs), (ins calltarget:$func, variable_ops), + (outs), (ins calltarget:$func), "bl $func", BrB, []>; // See Pat patterns below. let isCodeGenOnly = 1 in def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, - (outs), (ins calltarget:$func, variable_ops), + (outs), (ins calltarget:$func), "bl $func\n\tnop", BrB, []>; def BLA8_ELF : IForm<18, 1, 1, - (outs), (ins aaddr:$func, variable_ops), + (outs), (ins aaddr:$func), "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; let isCodeGenOnly = 1 in def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, - (outs), (ins aaddr:$func, variable_ops), + (outs), (ins aaddr:$func), "bla $func\n\tnop", BrB, [(PPCcall_nop_SVR4 (i64 imm:$func))]>; } let Uses = [X11, CTR8, RM] in { def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, - (outs), (ins variable_ops), + (outs), (ins), "bctrl", BrB, [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; } @@ -180,17 +180,17 @@ def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in def TCRETURNdi8 :Pseudo< (outs), - (ins calltarget:$dst, i32imm:$offset, variable_ops), + (ins calltarget:$dst, i32imm:$offset), "#TC_RETURNd8 $dst $offset", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in -def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), +def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), "#TC_RETURNa8 $func $offset", [(PPCtc_return (i64 imm:$func), imm:$offset)]>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in -def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), +def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), "#TC_RETURNr8 $dst $offset", []>; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 9b390461d8d7..f57f0c975ad6 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -452,15 +452,15 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { // Convenient aliases for call instructions let Uses = [RM] in { def BL_Darwin : IForm<18, 0, 1, - (outs), (ins calltarget:$func, variable_ops), + (outs), (ins calltarget:$func), "bl $func", BrB, []>; // See Pat patterns below. def BLA_Darwin : IForm<18, 1, 1, - (outs), (ins aaddr:$func, variable_ops), + (outs), (ins aaddr:$func), "bla $func", BrB, [(PPCcall_Darwin (i32 imm:$func))]>; } let Uses = [CTR, RM] in { def BCTRL_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, - (outs), (ins variable_ops), + (outs), (ins), "bctrl", BrB, [(PPCbctrl_Darwin)]>, Requires<[In32BitMode]>; } @@ -471,16 +471,16 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { // Convenient aliases for call instructions let Uses = [RM] in { def BL_SVR4 : IForm<18, 0, 1, - (outs), (ins calltarget:$func, variable_ops), + (outs), (ins calltarget:$func), "bl $func", BrB, []>; // See Pat patterns below. def BLA_SVR4 : IForm<18, 1, 1, - (outs), (ins aaddr:$func, variable_ops), + (outs), (ins aaddr:$func), "bla $func", BrB, [(PPCcall_SVR4 (i32 imm:$func))]>; } let Uses = [CTR, RM] in { def BCTRL_SVR4 : XLForm_2_ext<19, 528, 20, 0, 1, - (outs), (ins variable_ops), + (outs), (ins), "bctrl", BrB, [(PPCbctrl_SVR4)]>, Requires<[In32BitMode]>; } @@ -489,18 +489,18 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR] in { let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in def TCRETURNdi :Pseudo< (outs), - (ins calltarget:$dst, i32imm:$offset, variable_ops), + (ins calltarget:$dst, i32imm:$offset), "#TC_RETURNd $dst $offset", []>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in -def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), +def TCRETURNai :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), "#TC_RETURNa $func $offset", [(PPCtc_return (i32 imm:$func), imm:$offset)]>; let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in -def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset, variable_ops), +def TCRETURNri : Pseudo<(outs), (ins CTRRC:$dst, i32imm:$offset), "#TC_RETURNr $dst $offset", []>; diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.td b/llvm/lib/Target/XCore/XCoreInstrInfo.td index b2f060377688..f6f15309eccf 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.td +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.td @@ -741,14 +741,12 @@ let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { def BL_u10 : _FU10< - (outs), - (ins calltarget:$target, variable_ops), + (outs), (ins calltarget:$target), "bl $target", [(XCoreBranchLink immU10:$target)]>; def BL_lu10 : _FLU10< - (outs), - (ins calltarget:$target, variable_ops), + (outs), (ins calltarget:$target), "bl $target", [(XCoreBranchLink immU20:$target)]>; } @@ -988,7 +986,7 @@ def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { -def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), +def BLA_1r : _F1R<(outs), (ins GRRegs:$addr), "bla $addr", [(XCoreBranchLink GRRegs:$addr)]>; }