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Replace string GNU Triples with llvm::Triple in computeDataLayout(). NFC. 

Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, jfb, rengolin

Differential Revision: http://reviews.llvm.org/D10361

llvm-svn: 239538
This commit is contained in:
Daniel Sanders 2015-06-11 15:34:59 +00:00
parent fd5286717c
commit ed64d62c70
5 changed files with 24 additions and 27 deletions
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9
llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
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@ -115,9 +115,8 @@ static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
} }
// Helper function to build a DataLayout string // Helper function to build a DataLayout string
static std::string computeDataLayout(StringRef TT, bool LittleEndian) { static std::string computeDataLayout(const Triple &TT, bool LittleEndian) {
Triple Triple(TT); if (TT.isOSBinFormatMachO())
if (Triple.isOSBinFormatMachO())
return "e-m:o-i64:64-i128:128-n32:64-S128"; return "e-m:o-i64:64-i128:128-n32:64-S128";
if (LittleEndian) if (LittleEndian)
return "e-m:e-i64:64-i128:128-n32:64-S128"; return "e-m:e-i64:64-i128:128-n32:64-S128";
@ -134,8 +133,8 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, StringRef TT,
bool LittleEndian) bool LittleEndian)
// This nested ternary is horrible, but DL needs to be properly // This nested ternary is horrible, but DL needs to be properly
// initialized before TLInfo is constructed. // initialized before TLInfo is constructed.
: LLVMTargetMachine(T, computeDataLayout(TT, LittleEndian), TT, CPU, FS, : LLVMTargetMachine(T, computeDataLayout(Triple(TT), LittleEndian), TT, CPU,
Options, RM, CM, OL), FS, Options, RM, CM, OL),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
isLittle(LittleEndian) { isLittle(LittleEndian) {
initAsmInfo(); initAsmInfo();

14
llvm/lib/Target/ARM/ARMTargetMachine.cpp
View File

@ -115,11 +115,10 @@ computeTargetABI(const Triple &TT, StringRef CPU,
return TargetABI; return TargetABI;
} }
static std::string computeDataLayout(StringRef TT, StringRef CPU, static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options, const TargetOptions &Options,
bool isLittle) { bool isLittle) {
const Triple Triple(TT); auto ABI = computeTargetABI(TT, CPU, Options);
auto ABI = computeTargetABI(Triple, CPU, Options);
std::string Ret = ""; std::string Ret = "";
if (isLittle) if (isLittle)
@ -129,7 +128,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU,
// Big endian. // Big endian.
Ret += "E"; Ret += "E";
Ret += DataLayout::getManglingComponent(Triple); Ret += DataLayout::getManglingComponent(TT);
// Pointers are 32 bits and aligned to 32 bits. // Pointers are 32 bits and aligned to 32 bits.
Ret += "-p:32:32"; Ret += "-p:32:32";
@ -159,7 +158,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU,
// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit // The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
// aligned everywhere else. // aligned everywhere else.
if (Triple.isOSNaCl()) if (TT.isOSNaCl())
Ret += "-S128"; Ret += "-S128";
else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS) else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
Ret += "-S64"; Ret += "-S64";
@ -176,8 +175,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, : LLVMTargetMachine(T,
CPU, FS, Options, RM, CM, OL), computeDataLayout(Triple(TT), CPU, Options, isLittle),
TT, CPU, FS, Options, RM, CM, OL),
TargetABI(computeTargetABI(Triple(TT), CPU, Options)), TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
TLOF(createTLOF(Triple(getTargetTriple()))), TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) { Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) {

10
llvm/lib/Target/Mips/MipsTargetMachine.cpp
View File

@ -44,12 +44,11 @@ extern "C" void LLVMInitializeMipsTarget() {
RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget); RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
} }
static std::string computeDataLayout(StringRef TT, StringRef CPU, static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options, const TargetOptions &Options,
bool isLittle) { bool isLittle) {
std::string Ret = ""; std::string Ret = "";
MipsABIInfo ABI = MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions);
// There are both little and big endian mips. // There are both little and big endian mips.
if (isLittle) if (isLittle)
@ -88,8 +87,9 @@ MipsTargetMachine::MipsTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle) CodeGenOpt::Level OL, bool isLittle)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, : LLVMTargetMachine(T,
CPU, FS, Options, RM, CM, OL), computeDataLayout(Triple(TT), CPU, Options, isLittle),
TT, CPU, FS, Options, RM, CM, OL),
isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()), isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)), ABI(MipsABIInfo::computeTargetABI(Triple(TT), CPU, Options.MCOptions)),
Subtarget(nullptr), Subtarget(nullptr),

9
llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -51,11 +51,10 @@ static MachineSchedRegistry
SchedCustomRegistry("r600", "Run R600's custom scheduler", SchedCustomRegistry("r600", "Run R600's custom scheduler",
createR600MachineScheduler); createR600MachineScheduler);
static std::string computeDataLayout(StringRef TT) { static std::string computeDataLayout(const Triple &TT) {
Triple Triple(TT);
std::string Ret = "e-p:32:32"; std::string Ret = "e-p:32:32";
if (Triple.getArch() == Triple::amdgcn) { if (TT.getArch() == Triple::amdgcn) {
// 32-bit private, local, and region pointers. 64-bit global and constant. // 32-bit private, local, and region pointers. 64-bit global and constant.
Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"; Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
} }
@ -71,8 +70,8 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, StringRef TT,
TargetOptions Options, Reloc::Model RM, TargetOptions Options, Reloc::Model RM,
CodeModel::Model CM, CodeModel::Model CM,
CodeGenOpt::Level OptLevel) CodeGenOpt::Level OptLevel)
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM, : LLVMTargetMachine(T, computeDataLayout(Triple(TT)), TT, CPU, FS, Options,
OptLevel), RM, CM, OptLevel),
TLOF(new TargetLoweringObjectFileELF()), TLOF(new TargetLoweringObjectFileELF()),
Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() { Subtarget(Triple(TT), CPU, FS, *this), IntrinsicInfo() {
setRequiresStructuredCFG(true); setRequiresStructuredCFG(true);

9
llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp
View File

@ -43,9 +43,8 @@ static bool UsesVectorABI(StringRef CPU, StringRef FS) {
return VectorABI; return VectorABI;
} }
static std::string computeDataLayout(StringRef TT, StringRef CPU, static std::string computeDataLayout(const Triple &TT, StringRef CPU,
StringRef FS) { StringRef FS) {
const Triple Triple(TT);
bool VectorABI = UsesVectorABI(CPU, FS); bool VectorABI = UsesVectorABI(CPU, FS);
std::string Ret = ""; std::string Ret = "";
@ -53,7 +52,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU,
Ret += "E"; Ret += "E";
// Data mangling. // Data mangling.
Ret += DataLayout::getManglingComponent(Triple); Ret += DataLayout::getManglingComponent(TT);
// Make sure that global data has at least 16 bits of alignment by // Make sure that global data has at least 16 bits of alignment by
// default, so that we can refer to it using LARL. We don't have any // default, so that we can refer to it using LARL. We don't have any
@ -84,8 +83,8 @@ SystemZTargetMachine::SystemZTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options, const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL) CodeGenOpt::Level OL)
: LLVMTargetMachine(T, computeDataLayout(TT, CPU, FS), TT, CPU, FS, Options, : LLVMTargetMachine(T, computeDataLayout(Triple(TT), CPU, FS), TT, CPU, FS,
RM, CM, OL), Options, RM, CM, OL),
TLOF(make_unique<TargetLoweringObjectFileELF>()), TLOF(make_unique<TargetLoweringObjectFileELF>()),
Subtarget(Triple(TT), CPU, FS, *this) { Subtarget(Triple(TT), CPU, FS, *this) {
initAsmInfo(); initAsmInfo();