[RISCV] Implement MC layer support for the fence.tso instruction

The instruction makes use of a previously ignored field in the fence
instruction. It is introduced in the version 2.3 draft of the RISC-V
specification after much work by the Memory Model Task Group.

As clarified here <https://github.com/riscv/riscv-isa-manual/issues/186>,
the fence.tso assembler mnemonic does not have operands.

llvm-svn: 334278

llvm/lib/Target/RISCV/RISCVInstrInfo.td

@@ -350,6 +350,12 @@ def FENCE : RVInstI<0b000, OPC_MISC_MEM, (outs),
   let imm12 = {0b0000,pred,succ};
 }
 
+def FENCE_TSO : RVInstI<0b000, OPC_MISC_MEM, (outs), (ins), "fence.tso", ""> {
+  let rs1 = 0;
+  let rd = 0;
+  let imm12 = {0b1000,0b0011,0b0011};
+}
+
 def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", ""> {
   let rs1 = 0;
   let rd = 0;

llvm/test/MC/RISCV/rv32i-invalid.s

@@ -146,3 +146,6 @@ fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction use requires an o
 
 # Using floating point registers when integer registers are expected
 addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
+
+# fence.tso accepts no operands
+fence.tso rw, rw # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/test/MC/RISCV/rv32i-valid.s

@@ -205,6 +205,9 @@ fence r,w
 # CHECK-INST: fence w, ir
 # CHECK: encoding: [0x0f,0x00,0xa0,0x01]
 fence w,ir
+# CHECK-INST: fence.tso
+# CHECK: encoding: [0x0f,0x00,0x30,0x83]
+fence.tso
 
 # CHECK-INST: fence.i
 # CHECK: encoding: [0x0f,0x10,0x00,0x00]