forked from OSchip/llvm-project
GlobalISel: Start defining strict FP instructions
The AMDGPU lowering for unconstrained G_FDIV sometimes needs to introduce a mode switch in the middle, so it's helpful to have constrained instructions available to legalize this. Right now nothing is preventing reordering of the mode switch with the other instructions in the expansion.
This commit is contained in:
Matt Arsenault
Matt Arsenault
parent
ccb3c8e861
commit
ed5017e153
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@ -236,6 +236,9 @@ private:
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bool translateSimpleIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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MachineIRBuilder &MIRBuilder);
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bool translateConstrainedFPIntrinsic(const ConstrainedFPIntrinsic &FPI,
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MachineIRBuilder &MIRBuilder);
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bool translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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MachineIRBuilder &MIRBuilder);
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@ -640,6 +640,15 @@ HANDLE_TARGET_OPCODE(G_JUMP_TABLE)
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/// Generic dynamic stack allocation.
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HANDLE_TARGET_OPCODE(G_DYN_STACKALLOC)
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/// Strict floating point instructions.
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HANDLE_TARGET_OPCODE(G_STRICT_FADD)
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HANDLE_TARGET_OPCODE(G_STRICT_FSUB)
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HANDLE_TARGET_OPCODE(G_STRICT_FMUL)
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HANDLE_TARGET_OPCODE(G_STRICT_FDIV)
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HANDLE_TARGET_OPCODE(G_STRICT_FREM)
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HANDLE_TARGET_OPCODE(G_STRICT_FMA)
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HANDLE_TARGET_OPCODE(G_STRICT_FSQRT)
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/// read_register intrinsic
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HANDLE_TARGET_OPCODE(G_READ_REGISTER)
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@ -19,6 +19,22 @@ class GenericInstruction : StandardPseudoInstruction {
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let isPreISelOpcode = 1;
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}
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// Provide a variant of an instruction with the same operands, but
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// different instruction flags. This is intended to provide a
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// convenient way to define strict floating point variants of ordinary
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// floating point instructions.
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class ConstrainedIntruction<GenericInstruction baseInst> :
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GenericInstruction {
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let OutOperandList = baseInst.OutOperandList;
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let InOperandList = baseInst.InOperandList;
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let isCommutable = baseInst.isCommutable;
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// TODO: Do we need a better way to mark reads from FP mode than
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// hasSideEffects?
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let hasSideEffects = 1;
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let mayRaiseFPException = 1;
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}
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// Extend the underlying scalar type of an operation, leaving the high bits
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// unspecified.
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def G_ANYEXT : GenericInstruction {
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@ -1128,4 +1144,14 @@ def G_SHUFFLE_VECTOR: GenericInstruction {
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let hasSideEffects = 0;
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}
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// TODO: Add the other generic opcodes.
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//------------------------------------------------------------------------------
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// Constrained floating point ops
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//------------------------------------------------------------------------------
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def G_STRICT_FADD : ConstrainedIntruction<G_FADD>;
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def G_STRICT_FSUB : ConstrainedIntruction<G_FSUB>;
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def G_STRICT_FMUL : ConstrainedIntruction<G_FMUL>;
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def G_STRICT_FDIV : ConstrainedIntruction<G_FDIV>;
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def G_STRICT_FREM : ConstrainedIntruction<G_FREM>;
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def G_STRICT_FMA : ConstrainedIntruction<G_FMA>;
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def G_STRICT_FSQRT : ConstrainedIntruction<G_FSQRT>;
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@ -124,6 +124,14 @@ def : GINodeEquiv<G_FMINNUM_IEEE, fminnum_ieee>;
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def : GINodeEquiv<G_FMAXNUM_IEEE, fmaxnum_ieee>;
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def : GINodeEquiv<G_READCYCLECOUNTER, readcyclecounter>;
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def : GINodeEquiv<G_STRICT_FADD, strict_fadd>;
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def : GINodeEquiv<G_STRICT_FSUB, strict_fsub>;
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def : GINodeEquiv<G_STRICT_FMUL, strict_fmul>;
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def : GINodeEquiv<G_STRICT_FDIV, strict_fdiv>;
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def : GINodeEquiv<G_STRICT_FREM, strict_frem>;
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def : GINodeEquiv<G_STRICT_FMA, strict_fma>;
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def : GINodeEquiv<G_STRICT_FSQRT, strict_fsqrt>;
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// Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
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// complications that tablegen must take care of. For example, Predicates such
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// as isSignExtLoad require that this is not a perfect 1:1 mapping since a
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@ -1307,6 +1307,51 @@ bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
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return true;
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}
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// TODO: Include ConstainedOps.def when all strict instructions are defined.
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static unsigned getConstrainedOpcode(Intrinsic::ID ID) {
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switch (ID) {
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case Intrinsic::experimental_constrained_fadd:
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return TargetOpcode::G_STRICT_FADD;
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case Intrinsic::experimental_constrained_fsub:
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return TargetOpcode::G_STRICT_FSUB;
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case Intrinsic::experimental_constrained_fmul:
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return TargetOpcode::G_STRICT_FMUL;
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case Intrinsic::experimental_constrained_fdiv:
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return TargetOpcode::G_STRICT_FDIV;
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case Intrinsic::experimental_constrained_frem:
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return TargetOpcode::G_STRICT_FREM;
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case Intrinsic::experimental_constrained_fma:
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return TargetOpcode::G_STRICT_FMA;
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case Intrinsic::experimental_constrained_sqrt:
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return TargetOpcode::G_STRICT_FSQRT;
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default:
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return 0;
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}
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}
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bool IRTranslator::translateConstrainedFPIntrinsic(
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const ConstrainedFPIntrinsic &FPI, MachineIRBuilder &MIRBuilder) {
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fp::ExceptionBehavior EB = FPI.getExceptionBehavior().getValue();
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unsigned Opcode = getConstrainedOpcode(FPI.getIntrinsicID());
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if (!Opcode)
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return false;
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unsigned Flags = MachineInstr::copyFlagsFromInstruction(FPI);
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if (EB == fp::ExceptionBehavior::ebIgnore)
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Flags |= MachineInstr::NoFPExcept;
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SmallVector<llvm::SrcOp, 4> VRegs;
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VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(0)));
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if (!FPI.isUnaryOp())
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VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(1)));
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if (FPI.isTernaryOp())
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VRegs.push_back(getOrCreateVReg(*FPI.getArgOperand(2)));
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MIRBuilder.buildInstr(Opcode, {getOrCreateVReg(FPI)}, VRegs, Flags);
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return true;
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}
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bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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MachineIRBuilder &MIRBuilder) {
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@ -1572,6 +1617,12 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
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.addUse(getOrCreateVReg(*CI.getArgOperand(1)));
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return true;
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}
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#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
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case Intrinsic::INTRINSIC:
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#include "llvm/IR/ConstrainedOps.def"
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return translateConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(CI),
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MIRBuilder);
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}
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return false;
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}
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@ -0,0 +1,243 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -global-isel -march=amdgcn -stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
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define float @v_constained_fadd_f32_fpexcept_strict(float %x, float %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_f32_fpexcept_strict
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[STRICT_FADD:%[0-9]+]]:_(s32) = G_STRICT_FADD [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY [[STRICT_FADD]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%val = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
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ret float %val
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}
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define float @v_constained_fadd_f32_fpexcept_strict_flags(float %x, float %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_f32_fpexcept_strict_flags
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[STRICT_FADD:%[0-9]+]]:_(s32) = nsz G_STRICT_FADD [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY [[STRICT_FADD]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%val = call nsz float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
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ret float %val
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}
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define float @v_constained_fadd_f32_fpexcept_ignore(float %x, float %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_f32_fpexcept_ignore
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: %3:_(s32) = nofpexcept G_STRICT_FADD [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY %3(s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%val = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
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ret float %val
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}
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define float @v_constained_fadd_f32_fpexcept_ignore_flags(float %x, float %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_f32_fpexcept_ignore_flags
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: %3:_(s32) = nsz nofpexcept G_STRICT_FADD [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY %3(s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%val = call nsz float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
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ret float %val
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}
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define float @v_constained_fadd_f32_fpexcept_maytrap(float %x, float %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_f32_fpexcept_maytrap
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[STRICT_FADD:%[0-9]+]]:_(s32) = G_STRICT_FADD [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY [[STRICT_FADD]](s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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%val = call float @llvm.experimental.constrained.fadd.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
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ret float %val
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}
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define <2 x float> @v_constained_fadd_v2f32_fpexcept_strict(<2 x float> %x, <2 x float> %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_strict
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<2 x s32>)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
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; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
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%val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.strict")
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ret <2 x float> %val
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}
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define <2 x float> @v_constained_fadd_v2f32_fpexcept_ignore(<2 x float> %x, <2 x float> %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_ignore
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: %7:_(<2 x s32>) = nofpexcept G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES %7(<2 x s32>)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
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; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
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%val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
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ret <2 x float> %val
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}
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define <2 x float> @v_constained_fadd_v2f32_fpexcept_maytrap(<2 x float> %x, <2 x float> %y) #0 {
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; CHECK-LABEL: name: v_constained_fadd_v2f32_fpexcept_maytrap
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
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; CHECK: [[COPY4:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32)
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; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32)
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; CHECK: [[STRICT_FADD:%[0-9]+]]:_(<2 x s32>) = G_STRICT_FADD [[BUILD_VECTOR]], [[BUILD_VECTOR1]]
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; CHECK: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[STRICT_FADD]](<2 x s32>)
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; CHECK: $vgpr0 = COPY [[UV]](s32)
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; CHECK: $vgpr1 = COPY [[UV1]](s32)
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; CHECK: [[COPY5:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY4]]
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; CHECK: S_SETPC_B64_return [[COPY5]], implicit $vgpr0, implicit $vgpr1
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%val = call <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float> %x, <2 x float> %y, metadata !"round.tonearest", metadata !"fpexcept.maytrap")
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ret <2 x float> %val
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}
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define float @v_constained_fsub_f32_fpexcept_ignore_flags(float %x, float %y) #0 {
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; CHECK-LABEL: name: v_constained_fsub_f32_fpexcept_ignore_flags
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; CHECK: bb.1 (%ir-block.0):
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
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; CHECK: %3:_(s32) = nsz nofpexcept G_STRICT_FSUB [[COPY]], [[COPY1]]
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; CHECK: $vgpr0 = COPY %3(s32)
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; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
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; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
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||||
%val = call nsz float @llvm.experimental.constrained.fsub.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
|
||||
ret float %val
|
||||
}
|
||||
|
||||
define float @v_constained_fmul_f32_fpexcept_ignore_flags(float %x, float %y) #0 {
|
||||
; CHECK-LABEL: name: v_constained_fmul_f32_fpexcept_ignore_flags
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: %3:_(s32) = nsz nofpexcept G_STRICT_FMUL [[COPY]], [[COPY1]]
|
||||
; CHECK: $vgpr0 = COPY %3(s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
|
||||
%val = call nsz float @llvm.experimental.constrained.fmul.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
|
||||
ret float %val
|
||||
}
|
||||
|
||||
define float @v_constained_fdiv_f32_fpexcept_ignore_flags(float %x, float %y) #0 {
|
||||
; CHECK-LABEL: name: v_constained_fdiv_f32_fpexcept_ignore_flags
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: %3:_(s32) = nsz nofpexcept G_STRICT_FDIV [[COPY]], [[COPY1]]
|
||||
; CHECK: $vgpr0 = COPY %3(s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
|
||||
%val = call nsz float @llvm.experimental.constrained.fdiv.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
|
||||
ret float %val
|
||||
}
|
||||
|
||||
define float @v_constained_frem_f32_fpexcept_ignore_flags(float %x, float %y) #0 {
|
||||
; CHECK-LABEL: name: v_constained_frem_f32_fpexcept_ignore_flags
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: %3:_(s32) = nsz nofpexcept G_STRICT_FREM [[COPY]], [[COPY1]]
|
||||
; CHECK: $vgpr0 = COPY %3(s32)
|
||||
; CHECK: [[COPY3:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY2]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY3]], implicit $vgpr0
|
||||
%val = call nsz float @llvm.experimental.constrained.frem.f32(float %x, float %y, metadata !"round.tonearest", metadata !"fpexcept.ignore")
|
||||
ret float %val
|
||||
}
|
||||
|
||||
define float @v_constained_fma_f32_fpexcept_ignore_flags(float %x, float %y, float %z) #0 {
|
||||
; CHECK-LABEL: name: v_constained_fma_f32_fpexcept_ignore_flags
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
||||
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
||||
; CHECK: [[COPY3:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: %4:_(s32) = nsz nofpexcept G_STRICT_FMA [[COPY]], [[COPY1]], [[COPY2]]
|
||||
; CHECK: $vgpr0 = COPY %4(s32)
|
||||
; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY3]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0
|
||||
%val = call nsz float @llvm.experimental.constrained.fma.f32(float %x, float %y, float %z, metadata !"round.tonearest", metadata !"fpexcept.ignore")
|
||||
ret float %val
|
||||
}
|
||||
|
||||
define float @v_constained_sqrt_f32_fpexcept_strict(float %x) #0 {
|
||||
; CHECK-LABEL: name: v_constained_sqrt_f32_fpexcept_strict
|
||||
; CHECK: bb.1 (%ir-block.0):
|
||||
; CHECK: liveins: $vgpr0, $sgpr30_sgpr31
|
||||
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
||||
; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31
|
||||
; CHECK: [[STRICT_FSQRT:%[0-9]+]]:_(s32) = G_STRICT_FSQRT [[COPY]]
|
||||
; CHECK: $vgpr0 = COPY [[STRICT_FSQRT]](s32)
|
||||
; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]]
|
||||
; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0
|
||||
%val = call float @llvm.experimental.constrained.sqrt.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
|
||||
ret float %val
|
||||
}
|
||||
|
||||
declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata) #1
|
||||
declare <2 x float> @llvm.experimental.constrained.fadd.v2f32(<2 x float>, <2 x float>, metadata, metadata) #1
|
||||
declare <3 x float> @llvm.experimental.constrained.fadd.v3f32(<3 x float>, <3 x float>, metadata, metadata) #1
|
||||
declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata) #1
|
||||
declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata) #1
|
||||
declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata) #1
|
||||
declare float @llvm.experimental.constrained.frem.f32(float, float, metadata, metadata) #1
|
||||
declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata) #1
|
||||
declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata) #1
|
||||
|
||||
attributes #0 = { strictfp }
|
||||
attributes #1 = { inaccessiblememonly nounwind willreturn }
|
||||
Loading…
Reference in New Issue