From ed19bad61749170a489c033120737de0f53fc763 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Wed, 21 May 2014 23:40:18 +0000 Subject: [PATCH] Group the scheduling functions together. llvm-svn: 209339 --- llvm/include/llvm/Target/TargetSubtargetInfo.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/llvm/include/llvm/Target/TargetSubtargetInfo.h b/llvm/include/llvm/Target/TargetSubtargetInfo.h index 1b2e06acc2b0..e3febfb40f2b 100644 --- a/llvm/include/llvm/Target/TargetSubtargetInfo.h +++ b/llvm/include/llvm/Target/TargetSubtargetInfo.h @@ -76,6 +76,11 @@ public: MachineInstr *end, unsigned NumRegionInstrs) const {} + // \brief Perform target specific adjustments to the latency of a schedule + // dependency. + virtual void adjustSchedDependency(SUnit *def, SUnit *use, + SDep& dep) const { } + // enablePostRAScheduler - If the target can benefit from post-regalloc // scheduling and the specified optimization level meets the requirement // return true to enable post-register-allocation scheduling. In @@ -84,10 +89,6 @@ public: virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, AntiDepBreakMode& Mode, RegClassVector& CriticalPathRCs) const; - // adjustSchedDependency - Perform target specific adjustments to - // the latency of a schedule dependency. - virtual void adjustSchedDependency(SUnit *def, SUnit *use, - SDep& dep) const { } /// \brief Enable use of alias analysis during code generation (during MI /// scheduling, DAGCombine, etc.).