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[RISCV][test] Add new tests for mul optimization in the zba extension with SH*ADD 

This patch will show the following optimization by future patches.

(mul x imm) -> (SH1ADD x, (SLLI x, bits)) when imm = 2^n + 2.
(mul x imm) -> (SH2ADD x, (SLLI x, bits)) when imm = 2^n + 4.
(mul x imm) -> (SH3ADD x, (SLLI x, bits)) when imm = 2^n + 8.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D105614
This commit is contained in:
Ben Shi 2021-07-09 09:48:23 +08:00
parent 38451fa178
commit ed102ce20a
2 changed files with 132 additions and 0 deletions
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66
llvm/test/CodeGen/RISCV/rv32zba.ll
View File

@ -362,3 +362,69 @@ define i32 @mul288(i32 %a) {
%c = mul i32 %a, 288
ret i32 %c
}
define i32 @mul258(i32 %a) {
; RV32I-LABEL: mul258:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 258
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: mul258:
; RV32IB: # %bb.0:
; RV32IB-NEXT: addi a1, zero, 258
; RV32IB-NEXT: mul a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: mul258:
; RV32IBA: # %bb.0:
; RV32IBA-NEXT: addi a1, zero, 258
; RV32IBA-NEXT: mul a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 258
ret i32 %c
}
define i32 @mul260(i32 %a) {
; RV32I-LABEL: mul260:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 260
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: mul260:
; RV32IB: # %bb.0:
; RV32IB-NEXT: addi a1, zero, 260
; RV32IB-NEXT: mul a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: mul260:
; RV32IBA: # %bb.0:
; RV32IBA-NEXT: addi a1, zero, 260
; RV32IBA-NEXT: mul a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 260
ret i32 %c
}
define i32 @mul264(i32 %a) {
; RV32I-LABEL: mul264:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 264
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
; RV32IB-LABEL: mul264:
; RV32IB: # %bb.0:
; RV32IB-NEXT: addi a1, zero, 264
; RV32IB-NEXT: mul a0, a0, a1
; RV32IB-NEXT: ret
;
; RV32IBA-LABEL: mul264:
; RV32IBA: # %bb.0:
; RV32IBA-NEXT: addi a1, zero, 264
; RV32IBA-NEXT: mul a0, a0, a1
; RV32IBA-NEXT: ret
%c = mul i32 %a, 264
ret i32 %c
}

66
llvm/test/CodeGen/RISCV/rv64zba.ll
View File

@ -820,3 +820,69 @@ define i64 @adduw_imm(i32 signext %0) nounwind {
%b = add i64 %a, 5
ret i64 %b
}
define i64 @mul258(i64 %a) {
; RV64I-LABEL: mul258:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 258
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: mul258:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a1, zero, 258
; RV64IB-NEXT: mul a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: mul258:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a1, zero, 258
; RV64IBA-NEXT: mul a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 258
ret i64 %c
}
define i64 @mul260(i64 %a) {
; RV64I-LABEL: mul260:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 260
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: mul260:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a1, zero, 260
; RV64IB-NEXT: mul a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: mul260:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a1, zero, 260
; RV64IBA-NEXT: mul a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 260
ret i64 %c
}
define i64 @mul264(i64 %a) {
; RV64I-LABEL: mul264:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 264
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
; RV64IB-LABEL: mul264:
; RV64IB: # %bb.0:
; RV64IB-NEXT: addi a1, zero, 264
; RV64IB-NEXT: mul a0, a0, a1
; RV64IB-NEXT: ret
;
; RV64IBA-LABEL: mul264:
; RV64IBA: # %bb.0:
; RV64IBA-NEXT: addi a1, zero, 264
; RV64IBA-NEXT: mul a0, a0, a1
; RV64IBA-NEXT: ret
%c = mul i64 %a, 264
ret i64 %c
}