forked from OSchip/llvm-project
[X86] Teach fast isel to use MOV32ri64 for loading an unsigned 32 immediate into a 64-bit register.
Previously we used SUBREG_TO_REG+MOV32ri. But regular isel was changed recently to use the MOV32ri64 pseudo. Fast isel now does the same. llvm-svn: 342788
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@ -3744,7 +3744,7 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
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case MVT::i32: Opc = X86::MOV32ri; break;
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case MVT::i64: {
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if (isUInt<32>(Imm))
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Opc = X86::MOV32ri;
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Opc = X86::MOV32ri64;
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else if (isInt<32>(Imm))
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Opc = X86::MOV64ri32;
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else
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@ -3752,14 +3752,6 @@ unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) {
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break;
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}
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}
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if (VT == MVT::i64 && Opc == X86::MOV32ri) {
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unsigned SrcReg = fastEmitInst_i(Opc, &X86::GR32RegClass, Imm);
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unsigned ResultReg = createResultReg(&X86::GR64RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg)
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.addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
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return ResultReg;
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}
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return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm);
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}
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@ -67,9 +67,9 @@ define i64 @test__blsr_u64(i64 %a0) {
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define i64 @test__tzcnt_u64(i64 %a0) {
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; X64-LABEL: test__tzcnt_u64:
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; X64: # %bb.0:
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; X64-NEXT: movl $64, %ecx
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; X64-NEXT: tzcntq %rdi, %rax
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; X64-NEXT: cmovbq %rcx, %rax
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; X64-NEXT: tzcntq %rdi, %rcx
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; X64-NEXT: movl $64, %eax
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; X64-NEXT: cmovaeq %rcx, %rax
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; X64-NEXT: retq
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%cmp = icmp ne i64 %a0, 0
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%cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
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@ -151,9 +151,9 @@ define i64 @test_blsr_u64(i64 %a0) {
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define i64 @test_tzcnt_u64(i64 %a0) {
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; X64-LABEL: test_tzcnt_u64:
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; X64: # %bb.0:
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; X64-NEXT: movl $64, %ecx
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; X64-NEXT: tzcntq %rdi, %rax
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; X64-NEXT: cmovbq %rcx, %rax
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; X64-NEXT: tzcntq %rdi, %rcx
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; X64-NEXT: movl $64, %eax
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; X64-NEXT: cmovaeq %rcx, %rax
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; X64-NEXT: retq
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%cmp = icmp ne i64 %a0, 0
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%cttz = call i64 @llvm.cttz.i64(i64 %a0, i1 true)
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