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[X86][SSE] Regenerated HADD/HSUB tests 

llvm-svn: 257992
This commit is contained in:
Simon Pilgrim 2016-01-16 14:03:40 +00:00
parent 28eeb3f66c
commit ecd07946eb
4 changed files with 1421 additions and 471 deletions
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1017
llvm/test/CodeGen/X86/haddsub-2.ll
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File diff suppressed because it is too large Load Diff

319
llvm/test/CodeGen/X86/haddsub-undef.ll
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@ -1,10 +1,20 @@
; RUN: llc < %s -march=x86-64 -mattr=ssse3 | FileCheck %s -check-prefix=CHECK -check-prefix=SSE
; RUN: llc < %s -march=x86-64 -mattr=avx | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
; RUN: llc < %s -march=x86-64 -mattr=avx2 | FileCheck %s -check-prefix=CHECK -check-prefix=AVX2
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2
; Verify that we correctly fold horizontal binop even in the presence of UNDEFs.
define <4 x float> @test1_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test1_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test1_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %a, i32 0
%vecext1 = extractelement <4 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -19,14 +29,17 @@ define <4 x float> @test1_undef(<4 x float> %a, <4 x float> %b) {
%vecinit13 = insertelement <4 x float> %vecinit5, float %add12, i32 3
ret <4 x float> %vecinit13
}
; CHECK-LABEL: test1_undef
; SSE: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NEXT: ret
define <4 x float> @test2_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test2_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test2_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %a, i32 0
%vecext1 = extractelement <4 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -41,14 +54,17 @@ define <4 x float> @test2_undef(<4 x float> %a, <4 x float> %b) {
%vecinit13 = insertelement <4 x float> %vecinit9, float %add12, i32 3
ret <4 x float> %vecinit13
}
; CHECK-LABEL: test2_undef
; SSE: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NEXT: ret
define <4 x float> @test3_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test3_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test3_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %a, i32 0
%vecext1 = extractelement <4 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -63,38 +79,57 @@ define <4 x float> @test3_undef(<4 x float> %a, <4 x float> %b) {
%vecinit9 = insertelement <4 x float> %vecinit5, float %add8, i32 2
ret <4 x float> %vecinit9
}
; CHECK-LABEL: test3_undef
; SSE: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NEXT: ret
define <4 x float> @test4_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test4_undef:
; SSE: # BB#0:
; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test4_undef:
; AVX: # BB#0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %a, i32 0
%vecext1 = extractelement <4 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
%vecinit = insertelement <4 x float> undef, float %add, i32 0
ret <4 x float> %vecinit
}
; CHECK-LABEL: test4_undef
; CHECK-NOT: haddps
; CHECK: ret
define <2 x double> @test5_undef(<2 x double> %a, <2 x double> %b) {
; SSE-LABEL: test5_undef:
; SSE: # BB#0:
; SSE-NEXT: movapd %xmm0, %xmm1
; SSE-NEXT: shufpd {{.*#+}} xmm1 = xmm1[1,0]
; SSE-NEXT: addsd %xmm0, %xmm1
; SSE-NEXT: movapd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test5_undef:
; AVX: # BB#0:
; AVX-NEXT: vpermilpd {{.*#+}} xmm1 = xmm0[1,0]
; AVX-NEXT: vaddsd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <2 x double> %a, i32 0
%vecext1 = extractelement <2 x double> %a, i32 1
%add = fadd double %vecext, %vecext1
%vecinit = insertelement <2 x double> undef, double %add, i32 0
ret <2 x double> %vecinit
}
; CHECK-LABEL: test5_undef
; CHECK-NOT: haddpd
; CHECK: ret
define <4 x float> @test6_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test6_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test6_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %a, i32 0
%vecext1 = extractelement <4 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -105,14 +140,17 @@ define <4 x float> @test6_undef(<4 x float> %a, <4 x float> %b) {
%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 1
ret <4 x float> %vecinit5
}
; CHECK-LABEL: test6_undef
; SSE: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NEXT: ret
define <4 x float> @test7_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test7_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test7_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %b, i32 0
%vecext1 = extractelement <4 x float> %b, i32 1
%add = fadd float %vecext, %vecext1
@ -123,14 +161,30 @@ define <4 x float> @test7_undef(<4 x float> %a, <4 x float> %b) {
%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 3
ret <4 x float> %vecinit5
}
; CHECK-LABEL: test7_undef
; SSE: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NEXT: ret
define <4 x float> @test8_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test8_undef:
; SSE: # BB#0:
; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE-NEXT: addss %xmm0, %xmm1
; SSE-NEXT: movaps %xmm0, %xmm2
; SSE-NEXT: shufpd {{.*#+}} xmm2 = xmm2[1,0]
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; SSE-NEXT: addss %xmm2, %xmm0
; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1,1,3]
; SSE-NEXT: movaps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test8_undef:
; AVX: # BB#0:
; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; AVX-NEXT: vaddss %xmm1, %xmm0, %xmm1
; AVX-NEXT: vpermilpd {{.*#+}} xmm2 = xmm0[1,0]
; AVX-NEXT: vpermilps {{.*#+}} xmm0 = xmm0[3,1,2,3]
; AVX-NEXT: vaddss %xmm0, %xmm2, %xmm0
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm1[0,1],xmm0[0],xmm1[3]
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %a, i32 0
%vecext1 = extractelement <4 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -141,12 +195,17 @@ define <4 x float> @test8_undef(<4 x float> %a, <4 x float> %b) {
%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 2
ret <4 x float> %vecinit5
}
; CHECK-LABEL: test8_undef
; CHECK-NOT: haddps
; CHECK: ret
define <4 x float> @test9_undef(<4 x float> %a, <4 x float> %b) {
; SSE-LABEL: test9_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test9_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <4 x float> %a, i32 0
%vecext1 = extractelement <4 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -157,11 +216,17 @@ define <4 x float> @test9_undef(<4 x float> %a, <4 x float> %b) {
%vecinit5 = insertelement <4 x float> %vecinit, float %add4, i32 3
ret <4 x float> %vecinit5
}
; CHECK-LABEL: test9_undef
; CHECK: haddps
; CHECK-NEXT: ret
define <8 x float> @test10_undef(<8 x float> %a, <8 x float> %b) {
; SSE-LABEL: test10_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test10_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%vecext = extractelement <8 x float> %a, i32 0
%vecext1 = extractelement <8 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -172,14 +237,21 @@ define <8 x float> @test10_undef(<8 x float> %a, <8 x float> %b) {
%vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 3
ret <8 x float> %vecinit5
}
; CHECK-LABEL: test10_undef
; SSE: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NOT: haddps
; CHECK: ret
define <8 x float> @test11_undef(<8 x float> %a, <8 x float> %b) {
; SSE-LABEL: test11_undef:
; SSE: # BB#0:
; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]
; SSE-NEXT: addss %xmm1, %xmm0
; SSE-NEXT: movshdup {{.*#+}} xmm1 = xmm3[1,1,3,3]
; SSE-NEXT: addss %xmm3, %xmm1
; SSE-NEXT: movddup {{.*#+}} xmm1 = xmm1[0,0]
; SSE-NEXT: retq
;
; AVX-LABEL: test11_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %ymm0, %ymm0, %ymm0
; AVX-NEXT: retq
%vecext = extractelement <8 x float> %a, i32 0
%vecext1 = extractelement <8 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -190,13 +262,17 @@ define <8 x float> @test11_undef(<8 x float> %a, <8 x float> %b) {
%vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 6
ret <8 x float> %vecinit5
}
; CHECK-LABEL: test11_undef
; SSE-NOT: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK: ret
define <8 x float> @test12_undef(<8 x float> %a, <8 x float> %b) {
; SSE-LABEL: test12_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test12_undef:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %ymm0, %ymm0, %ymm0
; AVX-NEXT: retq
%vecext = extractelement <8 x float> %a, i32 0
%vecext1 = extractelement <8 x float> %a, i32 1
%add = fadd float %vecext, %vecext1
@ -207,14 +283,18 @@ define <8 x float> @test12_undef(<8 x float> %a, <8 x float> %b) {
%vecinit5 = insertelement <8 x float> %vecinit, float %add4, i32 1
ret <8 x float> %vecinit5
}
; CHECK-LABEL: test12_undef
; SSE: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NOT: haddps
; CHECK: ret
define <8 x float> @test13_undef(<8 x float> %a, <8 x float> %b) {
; SSE-LABEL: test13_undef:
; SSE: # BB#0:
; SSE-NEXT: haddps %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: test13_undef:
; AVX: # BB#0:
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%vecext = extractelement <8 x float> %a, i32 0
%vecext1 = extractelement <8 x float> %a, i32 1
%add1 = fadd float %vecext, %vecext1
@ -233,15 +313,22 @@ define <8 x float> @test13_undef(<8 x float> %a, <8 x float> %b) {
%vecinit4 = insertelement <8 x float> %vecinit3, float %add4, i32 3
ret <8 x float> %vecinit4
}
; CHECK-LABEL: test13_undef
; SSE: haddps
; SSE-NOT: haddps
; AVX: vhaddps
; AVX2: vhaddps
; CHECK-NOT: haddps
; CHECK: ret
define <8 x i32> @test14_undef(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: test14_undef:
; SSE: # BB#0:
; SSE-NEXT: phaddd %xmm2, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: test14_undef:
; AVX1: # BB#0:
; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: test14_undef:
; AVX2: # BB#0:
; AVX2-NEXT: vphaddd %ymm1, %ymm0, %ymm0
; AVX2-NEXT: retq
%vecext = extractelement <8 x i32> %a, i32 0
%vecext1 = extractelement <8 x i32> %a, i32 1
%add = add i32 %vecext, %vecext1
@ -252,17 +339,45 @@ define <8 x i32> @test14_undef(<8 x i32> %a, <8 x i32> %b) {
%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 3
ret <8 x i32> %vecinit5
}
; CHECK-LABEL: test14_undef
; SSE: phaddd
; AVX: vphaddd
; AVX2: vphaddd
; CHECK-NOT: phaddd
; CHECK: ret
; On AVX2, the following sequence can be folded into a single horizontal add.
; If the Subtarget doesn't support AVX2, then we avoid emitting two packed
; integer horizontal adds instead of two scalar adds followed by vector inserts.
define <8 x i32> @test15_undef(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: test15_undef:
; SSE: # BB#0:
; SSE-NEXT: movd %xmm0, %eax
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; SSE-NEXT: movd %xmm0, %ecx
; SSE-NEXT: addl %eax, %ecx
; SSE-NEXT: movd %xmm3, %eax
; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,1,2,3]
; SSE-NEXT: movd %xmm0, %edx
; SSE-NEXT: addl %eax, %edx
; SSE-NEXT: movd %ecx, %xmm0
; SSE-NEXT: movd %edx, %xmm1
; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; SSE-NEXT: retq
;
; AVX1-LABEL: test15_undef:
; AVX1: # BB#0:
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: vpextrd $1, %xmm0, %ecx
; AVX1-NEXT: addl %eax, %ecx
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0
; AVX1-NEXT: vmovd %xmm0, %eax
; AVX1-NEXT: vpextrd $1, %xmm0, %edx
; AVX1-NEXT: addl %eax, %edx
; AVX1-NEXT: vmovd %ecx, %xmm0
; AVX1-NEXT: vmovd %edx, %xmm1
; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[0,1,0,1]
; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: test15_undef:
; AVX2: # BB#0:
; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0
; AVX2-NEXT: retq
%vecext = extractelement <8 x i32> %a, i32 0
%vecext1 = extractelement <8 x i32> %a, i32 1
%add = add i32 %vecext, %vecext1
@ -273,13 +388,22 @@ define <8 x i32> @test15_undef(<8 x i32> %a, <8 x i32> %b) {
%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 6
ret <8 x i32> %vecinit5
}
; CHECK-LABEL: test15_undef
; SSE-NOT: phaddd
; AVX-NOT: vphaddd
; AVX2: vphaddd
; CHECK: ret
define <8 x i32> @test16_undef(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: test16_undef:
; SSE: # BB#0:
; SSE-NEXT: phaddd %xmm0, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: test16_undef:
; AVX1: # BB#0:
; AVX1-NEXT: vphaddd %xmm0, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: test16_undef:
; AVX2: # BB#0:
; AVX2-NEXT: vphaddd %ymm0, %ymm0, %ymm0
; AVX2-NEXT: retq
%vecext = extractelement <8 x i32> %a, i32 0
%vecext1 = extractelement <8 x i32> %a, i32 1
%add = add i32 %vecext, %vecext1
@ -290,14 +414,24 @@ define <8 x i32> @test16_undef(<8 x i32> %a, <8 x i32> %b) {
%vecinit5 = insertelement <8 x i32> %vecinit, i32 %add4, i32 1
ret <8 x i32> %vecinit5
}
; CHECK-LABEL: test16_undef
; SSE: phaddd
; AVX: vphaddd
; AVX2: vphaddd
; CHECK-NOT: haddps
; CHECK: ret
define <8 x i32> @test17_undef(<8 x i32> %a, <8 x i32> %b) {
; SSE-LABEL: test17_undef:
; SSE: # BB#0:
; SSE-NEXT: phaddd %xmm1, %xmm0
; SSE-NEXT: retq
;
; AVX1-LABEL: test17_undef:
; AVX1: # BB#0:
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT: vphaddd %xmm1, %xmm0, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: test17_undef:
; AVX2: # BB#0:
; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT: vphaddd %xmm1, %xmm0, %xmm0
; AVX2-NEXT: retq
%vecext = extractelement <8 x i32> %a, i32 0
%vecext1 = extractelement <8 x i32> %a, i32 1
%add1 = add i32 %vecext, %vecext1
@ -316,10 +450,3 @@ define <8 x i32> @test17_undef(<8 x i32> %a, <8 x i32> %b) {
%vecinit4 = insertelement <8 x i32> %vecinit3, i32 %add4, i32 3
ret <8 x i32> %vecinit4
}
; CHECK-LABEL: test17_undef
; SSE: phaddd
; AVX: vphaddd
; AVX2: vphaddd
; CHECK-NOT: haddps
; CHECK: ret

353
llvm/test/CodeGen/X86/haddsub.ll
View File

@ -1,293 +1,392 @@
; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
; SSE3-LABEL: haddpd1:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
; AVX-LABEL: haddpd1:
; AVX: vhaddpd
define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
; SSE3-LABEL: haddpd1:
; SSE3: # BB#0:
; SSE3-NEXT: haddpd %xmm1, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddpd1:
; AVX: # BB#0:
; AVX-NEXT: vhaddpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
%r = fadd <2 x double> %a, %b
ret <2 x double> %r
}
; SSE3-LABEL: haddpd2:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
; AVX-LABEL: haddpd2:
; AVX: vhaddpd
define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
; SSE3-LABEL: haddpd2:
; SSE3: # BB#0:
; SSE3-NEXT: haddpd %xmm1, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddpd2:
; AVX: # BB#0:
; AVX-NEXT: vhaddpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
%b = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 2, i32 1>
%r = fadd <2 x double> %a, %b
ret <2 x double> %r
}
; SSE3-LABEL: haddpd3:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
; AVX-LABEL: haddpd3:
; AVX: vhaddpd
define <2 x double> @haddpd3(<2 x double> %x) {
; SSE3-LABEL: haddpd3:
; SSE3: # BB#0:
; SSE3-NEXT: haddpd %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddpd3:
; AVX: # BB#0:
; AVX-NEXT: vhaddpd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
%r = fadd <2 x double> %a, %b
ret <2 x double> %r
}
; SSE3-LABEL: haddps1:
; SSE3-NOT: vhaddps
; SSE3: haddps
; AVX-LABEL: haddps1:
; AVX: vhaddps
define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
; SSE3-LABEL: haddps1:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm1, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps1:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: haddps2:
; SSE3-NOT: vhaddps
; SSE3: haddps
; AVX-LABEL: haddps2:
; AVX: vhaddps
define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
; SSE3-LABEL: haddps2:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm1, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps2:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
%b = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: haddps3:
; SSE3-NOT: vhaddps
; SSE3: haddps
; AVX-LABEL: haddps3:
; AVX: vhaddps
define <4 x float> @haddps3(<4 x float> %x) {
; SSE3-LABEL: haddps3:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps3:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: haddps4:
; SSE3-NOT: vhaddps
; SSE3: haddps
; AVX-LABEL: haddps4:
; AVX: vhaddps
define <4 x float> @haddps4(<4 x float> %x) {
; SSE3-LABEL: haddps4:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps4:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: haddps5:
; SSE3-NOT: vhaddps
; SSE3: haddps
; AVX-LABEL: haddps5:
; AVX: vhaddps
define <4 x float> @haddps5(<4 x float> %x) {
; SSE3-LABEL: haddps5:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps5:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: haddps6:
; SSE3-NOT: vhaddps
; SSE3: haddps
; AVX-LABEL: haddps6:
; AVX: vhaddps
define <4 x float> @haddps6(<4 x float> %x) {
; SSE3-LABEL: haddps6:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps6:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: haddps7:
; SSE3-NOT: vhaddps
; SSE3: haddps
; AVX-LABEL: haddps7:
; AVX: vhaddps
define <4 x float> @haddps7(<4 x float> %x) {
; SSE3-LABEL: haddps7:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps7:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
%r = fadd <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: hsubpd1:
; SSE3-NOT: vhsubpd
; SSE3: hsubpd
; AVX-LABEL: hsubpd1:
; AVX: vhsubpd
define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
; SSE3-LABEL: hsubpd1:
; SSE3: # BB#0:
; SSE3-NEXT: hsubpd %xmm1, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: hsubpd1:
; AVX: # BB#0:
; AVX-NEXT: vhsubpd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
%r = fsub <2 x double> %a, %b
ret <2 x double> %r
}
; SSE3-LABEL: hsubpd2:
; SSE3-NOT: vhsubpd
; SSE3: hsubpd
; AVX-LABEL: hsubpd2:
; AVX: vhsubpd
define <2 x double> @hsubpd2(<2 x double> %x) {
; SSE3-LABEL: hsubpd2:
; SSE3: # BB#0:
; SSE3-NEXT: hsubpd %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: hsubpd2:
; AVX: # BB#0:
; AVX-NEXT: vhsubpd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
%r = fsub <2 x double> %a, %b
ret <2 x double> %r
}
; SSE3-LABEL: hsubps1:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; AVX-LABEL: hsubps1:
; AVX: vhsubps
define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
; SSE3-LABEL: hsubps1:
; SSE3: # BB#0:
; SSE3-NEXT: hsubps %xmm1, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: hsubps1:
; AVX: # BB#0:
; AVX-NEXT: vhsubps %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%r = fsub <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: hsubps2:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; AVX-LABEL: hsubps2:
; AVX: vhsubps
define <4 x float> @hsubps2(<4 x float> %x) {
; SSE3-LABEL: hsubps2:
; SSE3: # BB#0:
; SSE3-NEXT: hsubps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: hsubps2:
; AVX: # BB#0:
; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
%r = fsub <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: hsubps3:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; AVX-LABEL: hsubps3:
; AVX: vhsubps
define <4 x float> @hsubps3(<4 x float> %x) {
; SSE3-LABEL: hsubps3:
; SSE3: # BB#0:
; SSE3-NEXT: hsubps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: hsubps3:
; AVX: # BB#0:
; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
%r = fsub <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: hsubps4:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; AVX-LABEL: hsubps4:
; AVX: vhsubps
define <4 x float> @hsubps4(<4 x float> %x) {
; SSE3-LABEL: hsubps4:
; SSE3: # BB#0:
; SSE3-NEXT: hsubps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: hsubps4:
; AVX: # BB#0:
; AVX-NEXT: vhsubps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%r = fsub <4 x float> %a, %b
ret <4 x float> %r
}
; SSE3-LABEL: vhaddps1:
; SSE3-NOT: vhaddps
; SSE3: haddps
; SSE3: haddps
; AVX-LABEL: vhaddps1:
; AVX: vhaddps
define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
; SSE3-LABEL: vhaddps1:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm2, %xmm0
; SSE3-NEXT: haddps %xmm3, %xmm1
; SSE3-NEXT: retq
;
; AVX-LABEL: vhaddps1:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
%r = fadd <8 x float> %a, %b
ret <8 x float> %r
}
; SSE3-LABEL: vhaddps2:
; SSE3-NOT: vhaddps
; SSE3: haddps
; SSE3: haddps
; AVX-LABEL: vhaddps2:
; AVX: vhaddps
define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
; SSE3-LABEL: vhaddps2:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm2, %xmm0
; SSE3-NEXT: haddps %xmm3, %xmm1
; SSE3-NEXT: retq
;
; AVX-LABEL: vhaddps2:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
%b = shufflevector <8 x float> %y, <8 x float> %x, <8 x i32> <i32 8, i32 11, i32 0, i32 3, i32 12, i32 15, i32 4, i32 7>
%r = fadd <8 x float> %a, %b
ret <8 x float> %r
}
; SSE3-LABEL: vhaddps3:
; SSE3-NOT: vhaddps
; SSE3: haddps
; SSE3: haddps
; AVX-LABEL: vhaddps3:
; AVX: vhaddps
define <8 x float> @vhaddps3(<8 x float> %x) {
; SSE3-LABEL: vhaddps3:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: haddps %xmm1, %xmm1
; SSE3-NEXT: retq
;
; AVX-LABEL: vhaddps3:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %ymm0, %ymm0, %ymm0
; AVX-NEXT: retq
%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
%r = fadd <8 x float> %a, %b
ret <8 x float> %r
}
; SSE3-LABEL: vhsubps1:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; SSE3: hsubps
; AVX-LABEL: vhsubps1:
; AVX: vhsubps
define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
; SSE3-LABEL: vhsubps1:
; SSE3: # BB#0:
; SSE3-NEXT: hsubps %xmm2, %xmm0
; SSE3-NEXT: hsubps %xmm3, %xmm1
; SSE3-NEXT: retq
;
; AVX-LABEL: vhsubps1:
; AVX: # BB#0:
; AVX-NEXT: vhsubps %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
%b = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 3, i32 9, i32 11, i32 5, i32 7, i32 13, i32 15>
%r = fsub <8 x float> %a, %b
ret <8 x float> %r
}
; SSE3-LABEL: vhsubps3:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; SSE3: hsubps
; AVX-LABEL: vhsubps3:
; AVX: vhsubps
define <8 x float> @vhsubps3(<8 x float> %x) {
; SSE3-LABEL: vhsubps3:
; SSE3: # BB#0:
; SSE3-NEXT: hsubps %xmm0, %xmm0
; SSE3-NEXT: hsubps %xmm1, %xmm1
; SSE3-NEXT: retq
;
; AVX-LABEL: vhsubps3:
; AVX: # BB#0:
; AVX-NEXT: vhsubps %ymm0, %ymm0, %ymm0
; AVX-NEXT: retq
%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
%b = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 1, i32 3, i32 9, i32 undef, i32 5, i32 7, i32 13, i32 15>
%r = fsub <8 x float> %a, %b
ret <8 x float> %r
}
; SSE3-LABEL: vhaddpd1:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
; SSE3: haddpd
; AVX-LABEL: vhaddpd1:
; AVX: vhaddpd
define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
; SSE3-LABEL: vhaddpd1:
; SSE3: # BB#0:
; SSE3-NEXT: haddpd %xmm2, %xmm0
; SSE3-NEXT: haddpd %xmm3, %xmm1
; SSE3-NEXT: retq
;
; AVX-LABEL: vhaddpd1:
; AVX: # BB#0:
; AVX-NEXT: vhaddpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%r = fadd <4 x double> %a, %b
ret <4 x double> %r
}
; SSE3-LABEL: vhsubpd1:
; SSE3-NOT: vhsubpd
; SSE3: hsubpd
; SSE3: hsubpd
; AVX-LABEL: vhsubpd1:
; AVX: vhsubpd
define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
; SSE3-LABEL: vhsubpd1:
; SSE3: # BB#0:
; SSE3-NEXT: hsubpd %xmm2, %xmm0
; SSE3-NEXT: hsubpd %xmm3, %xmm1
; SSE3-NEXT: retq
;
; AVX-LABEL: vhsubpd1:
; AVX: # BB#0:
; AVX-NEXT: vhsubpd %ymm1, %ymm0, %ymm0
; AVX-NEXT: retq
%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
%b = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 5, i32 3, i32 7>
%r = fsub <4 x double> %a, %b
ret <4 x double> %r
}
; CHECK-LABEL: haddps_v2f32
; CHECK: haddps %xmm{{[0-9]+}}, %xmm0
; CHECK-NEXT: retq
define <2 x float> @haddps_v2f32(<4 x float> %v0) {
; SSE3-LABEL: haddps_v2f32:
; SSE3: # BB#0:
; SSE3-NEXT: haddps %xmm0, %xmm0
; SSE3-NEXT: retq
;
; AVX-LABEL: haddps_v2f32:
; AVX: # BB#0:
; AVX-NEXT: vhaddps %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%v0.0 = extractelement <4 x float> %v0, i32 0
%v0.1 = extractelement <4 x float> %v0, i32 1
%v0.2 = extractelement <4 x float> %v0, i32 2

201
llvm/test/CodeGen/X86/phaddsub.ll
View File

@ -1,168 +1,225 @@
; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSSE3
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
; SSSE3-LABEL: phaddw1:
; SSSE3-NOT: vphaddw
; SSSE3: phaddw
; AVX-LABEL: phaddw1:
; AVX: vphaddw
define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
; SSSE3-LABEL: phaddw1:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddw %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddw1:
; AVX: # BB#0:
; AVX-NEXT: vphaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%r = add <8 x i16> %a, %b
ret <8 x i16> %r
}
; SSSE3-LABEL: phaddw2:
; SSSE3-NOT: vphaddw
; SSSE3: phaddw
; AVX-LABEL: phaddw2:
; AVX: vphaddw
define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
; SSSE3-LABEL: phaddw2:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddw %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddw2:
; AVX: # BB#0:
; AVX-NEXT: vphaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14>
%b = shufflevector <8 x i16> %y, <8 x i16> %x, <8 x i32> <i32 8, i32 11, i32 12, i32 15, i32 0, i32 3, i32 4, i32 7>
%r = add <8 x i16> %a, %b
ret <8 x i16> %r
}
; SSSE3-LABEL: phaddd1:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
; AVX-LABEL: phaddd1:
; AVX: vphaddd
define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
; SSSE3-LABEL: phaddd1:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddd %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddd1:
; AVX: # BB#0:
; AVX-NEXT: vphaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%r = add <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phaddd2:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
; AVX-LABEL: phaddd2:
; AVX: vphaddd
define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
; SSSE3-LABEL: phaddd2:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddd %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddd2:
; AVX: # BB#0:
; AVX-NEXT: vphaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
%b = shufflevector <4 x i32> %y, <4 x i32> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
%r = add <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phaddd3:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
; AVX-LABEL: phaddd3:
; AVX: vphaddd
define <4 x i32> @phaddd3(<4 x i32> %x) {
; SSSE3-LABEL: phaddd3:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddd3:
; AVX: # BB#0:
; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
%r = add <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phaddd4:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
; AVX-LABEL: phaddd4:
; AVX: vphaddd
define <4 x i32> @phaddd4(<4 x i32> %x) {
; SSSE3-LABEL: phaddd4:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddd4:
; AVX: # BB#0:
; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
%r = add <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phaddd5:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
; AVX-LABEL: phaddd5:
; AVX: vphaddd
define <4 x i32> @phaddd5(<4 x i32> %x) {
; SSSE3-LABEL: phaddd5:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddd5:
; AVX: # BB#0:
; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
%r = add <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phaddd6:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
; AVX-LABEL: phaddd6:
; AVX: vphaddd
define <4 x i32> @phaddd6(<4 x i32> %x) {
; SSSE3-LABEL: phaddd6:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddd6:
; AVX: # BB#0:
; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%r = add <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phaddd7:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
; AVX-LABEL: phaddd7:
; AVX: vphaddd
define <4 x i32> @phaddd7(<4 x i32> %x) {
; SSSE3-LABEL: phaddd7:
; SSSE3: # BB#0:
; SSSE3-NEXT: phaddd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phaddd7:
; AVX: # BB#0:
; AVX-NEXT: vphaddd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
%r = add <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phsubw1:
; SSSE3-NOT: vphsubw
; SSSE3: phsubw
; AVX-LABEL: phsubw1:
; AVX: vphsubw
define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
; SSSE3-LABEL: phsubw1:
; SSSE3: # BB#0:
; SSSE3-NEXT: phsubw %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phsubw1:
; AVX: # BB#0:
; AVX-NEXT: vphsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%b = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%r = sub <8 x i16> %a, %b
ret <8 x i16> %r
}
; SSSE3-LABEL: phsubd1:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
; AVX-LABEL: phsubd1:
; AVX: vphsubd
define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
; SSSE3-LABEL: phsubd1:
; SSSE3: # BB#0:
; SSSE3-NEXT: phsubd %xmm1, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phsubd1:
; AVX: # BB#0:
; AVX-NEXT: vphsubd %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%b = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%r = sub <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phsubd2:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
; AVX-LABEL: phsubd2:
; AVX: vphsubd
define <4 x i32> @phsubd2(<4 x i32> %x) {
; SSSE3-LABEL: phsubd2:
; SSSE3: # BB#0:
; SSSE3-NEXT: phsubd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phsubd2:
; AVX: # BB#0:
; AVX-NEXT: vphsubd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
%r = sub <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phsubd3:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
; AVX-LABEL: phsubd3:
; AVX: vphsubd
define <4 x i32> @phsubd3(<4 x i32> %x) {
; SSSE3-LABEL: phsubd3:
; SSSE3: # BB#0:
; SSSE3-NEXT: phsubd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phsubd3:
; AVX: # BB#0:
; AVX-NEXT: vphsubd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
%r = sub <4 x i32> %a, %b
ret <4 x i32> %r
}
; SSSE3-LABEL: phsubd4:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
; AVX-LABEL: phsubd4:
; AVX: vphsubd
define <4 x i32> @phsubd4(<4 x i32> %x) {
; SSSE3-LABEL: phsubd4:
; SSSE3: # BB#0:
; SSSE3-NEXT: phsubd %xmm0, %xmm0
; SSSE3-NEXT: retq
;
; AVX-LABEL: phsubd4:
; AVX: # BB#0:
; AVX-NEXT: vphsubd %xmm0, %xmm0, %xmm0
; AVX-NEXT: retq
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
%b = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
%r = sub <4 x i32> %a, %b