forked from OSchip/llvm-project
[X86][AVX] lowerShuffleWithPERMV - adjust binary shuffle masks to account for widening on non-VLX targets
rGabd33bf5eff2 enabled us to pad 128/256-bit shuffles to 512-bit on non-VLX targets, but wasn't updating binary shuffles to account for the new vector width.
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667e800bb3
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@ -14951,16 +14951,27 @@ static SDValue lowerShuffleWithPERMV(const SDLoc &DL, MVT VT,
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ArrayRef<int> Mask, SDValue V1, SDValue V2,
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ArrayRef<int> Mask, SDValue V1, SDValue V2,
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const X86Subtarget &Subtarget,
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const X86Subtarget &Subtarget,
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SelectionDAG &DAG) {
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SelectionDAG &DAG) {
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int NumElts = VT.getVectorNumElements();
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MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
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MVT MaskEltVT = MVT::getIntegerVT(VT.getScalarSizeInBits());
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MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, VT.getVectorNumElements());
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MVT MaskVecVT = MVT::getVectorVT(MaskEltVT, NumElts);
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SDValue MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
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SDValue MaskNode;
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MVT ShuffleVT = VT;
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MVT ShuffleVT = VT;
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if (!VT.is512BitVector() && !Subtarget.hasVLX()) {
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if (!VT.is512BitVector() && !Subtarget.hasVLX()) {
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V1 = widenSubVector(V1, false, Subtarget, DAG, DL, 512);
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V1 = widenSubVector(V1, false, Subtarget, DAG, DL, 512);
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V2 = widenSubVector(V2, false, Subtarget, DAG, DL, 512);
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V2 = widenSubVector(V2, false, Subtarget, DAG, DL, 512);
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MaskNode = widenSubVector(MaskNode, false, Subtarget, DAG, DL, 512);
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ShuffleVT = V1.getSimpleValueType();
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ShuffleVT = V1.getSimpleValueType();
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// Adjust mask to correct indices for the second input.
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unsigned Scale = 512 / VT.getSizeInBits();
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SmallVector<int, 32> AdjustedMask(Mask.begin(), Mask.end());
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for (int &M : AdjustedMask)
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if (NumElts <= M)
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M += (Scale - 1) * NumElts;
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MaskNode = getConstVector(AdjustedMask, MaskVecVT, DAG, DL, true);
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MaskNode = widenSubVector(MaskNode, false, Subtarget, DAG, DL, 512);
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} else {
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MaskNode = getConstVector(Mask, MaskVecVT, DAG, DL, true);
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}
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}
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SDValue Result;
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SDValue Result;
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@ -85,9 +85,10 @@ define void @shuffle_v32i16_to_v16i16_1(<32 x i16>* %L, <16 x i16>* %S) nounwind
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;
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;
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; AVX512BW-LABEL: shuffle_v32i16_to_v16i16_1:
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; AVX512BW-LABEL: shuffle_v32i16_to_v16i16_1:
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; AVX512BW: # %bb.0:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = [1,3,5,7,17,19,21,23,9,11,13,15,25,27,29,31]
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = [1,3,5,7,33,35,37,39,9,11,13,15,41,43,45,47]
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vpermt2w %zmm0, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm2
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; AVX512BW-NEXT: vpermt2w %zmm2, %zmm0, %zmm1
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; AVX512BW-NEXT: vpermq {{.*#+}} ymm0 = ymm1[0,2,1,3]
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; AVX512BW-NEXT: vpermq {{.*#+}} ymm0 = ymm1[0,2,1,3]
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; AVX512BW-NEXT: vmovdqa %ymm0, (%rsi)
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; AVX512BW-NEXT: vmovdqa %ymm0, (%rsi)
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: vzeroupper
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@ -258,9 +259,10 @@ define void @shuffle_v32i16_to_v8i16_1(<32 x i16>* %L, <8 x i16>* %S) nounwind {
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;
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;
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; AVX512BW-LABEL: shuffle_v32i16_to_v8i16_1:
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; AVX512BW-LABEL: shuffle_v32i16_to_v8i16_1:
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; AVX512BW: # %bb.0:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <1,5,9,13,17,21,25,29,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <1,5,9,13,33,37,41,45,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vpermt2w %zmm0, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm2
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; AVX512BW-NEXT: vpermt2w %zmm2, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqa %xmm1, (%rsi)
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; AVX512BW-NEXT: vmovdqa %xmm1, (%rsi)
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: retq
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; AVX512BW-NEXT: retq
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@ -316,9 +318,10 @@ define void @shuffle_v32i16_to_v8i16_2(<32 x i16>* %L, <8 x i16>* %S) nounwind {
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;
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;
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; AVX512BW-LABEL: shuffle_v32i16_to_v8i16_2:
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; AVX512BW-LABEL: shuffle_v32i16_to_v8i16_2:
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; AVX512BW: # %bb.0:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <2,6,10,14,18,22,26,30,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <2,6,10,14,34,38,42,46,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vpermt2w %zmm0, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm2
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; AVX512BW-NEXT: vpermt2w %zmm2, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqa %xmm1, (%rsi)
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; AVX512BW-NEXT: vmovdqa %xmm1, (%rsi)
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: retq
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; AVX512BW-NEXT: retq
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@ -374,9 +377,10 @@ define void @shuffle_v32i16_to_v8i16_3(<32 x i16>* %L, <8 x i16>* %S) nounwind {
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;
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;
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; AVX512BW-LABEL: shuffle_v32i16_to_v8i16_3:
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; AVX512BW-LABEL: shuffle_v32i16_to_v8i16_3:
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; AVX512BW: # %bb.0:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <3,7,11,15,19,23,27,31,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <3,7,11,15,35,39,43,47,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vmovdqa (%rdi), %ymm1
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; AVX512BW-NEXT: vpermt2w %zmm0, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqa 32(%rdi), %ymm2
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; AVX512BW-NEXT: vpermt2w %zmm2, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqa %xmm1, (%rsi)
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; AVX512BW-NEXT: vmovdqa %xmm1, (%rsi)
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: vzeroupper
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; AVX512BW-NEXT: retq
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; AVX512BW-NEXT: retq
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@ -327,8 +327,8 @@ define <16 x i8> @trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_
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;
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;
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; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_61:
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; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_61:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI-NEXT: vmovdqa {{.*#+}} ymm1 = <1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512VBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,61]
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; AVX512VBMI-NEXT: vpermt2b %zmm0, %zmm1, %zmm0
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; AVX512VBMI-NEXT: vpermb %zmm0, %zmm1, %zmm0
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; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512VBMI-NEXT: vzeroupper
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; AVX512VBMI-NEXT: vzeroupper
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; AVX512VBMI-NEXT: retq
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; AVX512VBMI-NEXT: retq
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@ -412,8 +412,8 @@ define <16 x i8> @trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_
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;
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;
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; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:
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; AVX512VBMI-LABEL: trunc_shuffle_v64i8_01_05_09_13_17_21_25_29_33_37_41_45_49_53_57_62:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI-NEXT: vmovdqa {{.*#+}} ymm1 = <1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,62,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512VBMI-NEXT: vmovdqa {{.*#+}} xmm1 = [1,5,9,13,17,21,25,29,33,37,41,45,49,53,57,62]
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; AVX512VBMI-NEXT: vpermt2b %zmm0, %zmm1, %zmm0
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; AVX512VBMI-NEXT: vpermb %zmm0, %zmm1, %zmm0
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; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512VBMI-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
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; AVX512VBMI-NEXT: vzeroupper
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; AVX512VBMI-NEXT: vzeroupper
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; AVX512VBMI-NEXT: retq
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; AVX512VBMI-NEXT: retq
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@ -455,9 +455,10 @@ define <4 x double> @PR34175(<32 x i16>* %p) {
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;
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;
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; AVX512BW-LABEL: PR34175:
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; AVX512BW-LABEL: PR34175:
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; AVX512BW: # %bb.0:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <0,8,16,24,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm0 = <0,8,32,40,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512BW-NEXT: vmovdqu (%rdi), %ymm1
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; AVX512BW-NEXT: vmovdqu (%rdi), %ymm1
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; AVX512BW-NEXT: vpermt2w %zmm0, %zmm0, %zmm1
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; AVX512BW-NEXT: vmovdqu 32(%rdi), %ymm2
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; AVX512BW-NEXT: vpermt2w %zmm2, %zmm0, %zmm1
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; AVX512BW-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; AVX512BW-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; AVX512BW-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX512BW-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX512BW-NEXT: retq
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; AVX512BW-NEXT: retq
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@ -473,9 +474,10 @@ define <4 x double> @PR34175(<32 x i16>* %p) {
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;
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;
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; AVX512VBMI-LABEL: PR34175:
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; AVX512VBMI-LABEL: PR34175:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI-NEXT: vmovdqa {{.*#+}} ymm0 = <0,8,16,24,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512VBMI-NEXT: vmovdqa {{.*#+}} ymm0 = <0,8,32,40,u,u,u,u,u,u,u,u,u,u,u,u>
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; AVX512VBMI-NEXT: vmovdqu (%rdi), %ymm1
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; AVX512VBMI-NEXT: vmovdqu (%rdi), %ymm1
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; AVX512VBMI-NEXT: vpermt2w %zmm0, %zmm0, %zmm1
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; AVX512VBMI-NEXT: vmovdqu 32(%rdi), %ymm2
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; AVX512VBMI-NEXT: vpermt2w %zmm2, %zmm0, %zmm1
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; AVX512VBMI-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; AVX512VBMI-NEXT: vpmovzxwd {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
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; AVX512VBMI-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX512VBMI-NEXT: vcvtdq2pd %xmm0, %ymm0
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; AVX512VBMI-NEXT: retq
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; AVX512VBMI-NEXT: retq
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