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pr9367: Add missing predicated BLX instructions. 

Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915
This commit is contained in:
Bob Wilson 2011-03-03 01:41:01 +00:00
parent 8c68af9092
commit ec84568904
4 changed files with 27 additions and 4 deletions
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20
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -1340,7 +1340,16 @@ let isCall = 1,
Requires<[IsARM, HasV5T, IsNotDarwin]> { Requires<[IsARM, HasV5T, IsNotDarwin]> {
bits<4> func; bits<4> func;
let Inst{31-4} = 0b1110000100101111111111110011; let Inst{31-4} = 0b1110000100101111111111110011;
let Inst{3-0} = func; let Inst{3-0} = func;
}
def BLX_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
IIC_Br, "blx", "\t$func",
[(ARMcall_pred GPR:$func)]>,
Requires<[IsARM, HasV5T, IsNotDarwin]> {
bits<4> func;
let Inst{27-4} = 0b000100101111111111110011;
let Inst{3-0} = func;
} }
// ARMv4T // ARMv4T
@ -1389,6 +1398,15 @@ let isCall = 1,
let Inst{3-0} = func; let Inst{3-0} = func;
} }
def BLXr9_pred : AI<(outs), (ins GPR:$func, variable_ops), BrMiscFrm,
IIC_Br, "blx", "\t$func",
[(ARMcall_pred GPR:$func)]>,
Requires<[IsARM, HasV5T, IsDarwin]> {
bits<4> func;
let Inst{27-4} = 0b000100101111111111110011;
let Inst{3-0} = func;
}
// ARMv4T // ARMv4T
// Note: Restrict $func to the tGPR regclass to prevent it being in LR. // Note: Restrict $func to the tGPR regclass to prevent it being in LR.
def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops), def BXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),

6
llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -809,8 +809,10 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR) if (Opcode == ARM::BX_RET || Opcode == ARM::MOVPCLR)
return true; return true;
// BLXr9 and BX take one GPR reg. // BLX and BX take one GPR reg.
if (Opcode == ARM::BLXr9 || Opcode == ARM::BX) { if (Opcode == ARM::BLXr9 || Opcode == ARM::BLXr9_pred ||
Opcode == ARM::BLX || Opcode == ARM::BLX_pred ||
Opcode == ARM::BX) {
assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && assert(NumOps >= 1 && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
"Reg operand expected"); "Reg operand expected");
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,

3
llvm/test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -133,3 +133,6 @@
# CHECK: rsbs r6, r7, r8 # CHECK: rsbs r6, r7, r8
0x08 0x60 0x77 0xe0 0x08 0x60 0x77 0xe0
# CHECK: blxeq r5
0x35 0xff 0x2f 0x01

2
llvm/utils/TableGen/ARMDecoderEmitter.cpp
View File

@ -1632,7 +1632,7 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
// Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction. // Ignore the non-Darwin BL instructions and the TPsoft (TLS) instruction.
if (Name == "BL" || Name == "BL_pred" || Name == "BLX" || Name == "BX" || if (Name == "BL" || Name == "BL_pred" || Name == "BLX" || Name == "BX" ||
Name == "TPsoft") Name == "BLX_pred" || Name == "TPsoft")
return false; return false;
// Ignore VDUPf[d|q] instructions known to conflict with VDUP32[d-q] for // Ignore VDUPf[d|q] instructions known to conflict with VDUP32[d-q] for