forked from OSchip/llvm-project
Disable transformation of select of two loads to a select of address and then a load if the
loads are not in the default address space because the transformation discards src value info. llvm-svn: 93180
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@ -5792,35 +5792,48 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS,
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if (LLD->getMemoryVT() == RLD->getMemoryVT()) {
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// FIXME: this discards src value information. This is
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// over-conservative. It would be beneficial to be able to remember
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// both potential memory locations.
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// both potential memory locations. Since we are discarding
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// src value info, don't do the transformation if the memory
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// locations are not in the default address space.
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unsigned LLDAddrSpace = 0, RLDAddrSpace = 0;
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if (const Value *LLDVal = LLD->getMemOperand()->getValue()) {
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if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType()))
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LLDAddrSpace = PT->getAddressSpace();
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}
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if (const Value *RLDVal = RLD->getMemOperand()->getValue()) {
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if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType()))
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RLDAddrSpace = PT->getAddressSpace();
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}
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SDValue Addr;
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if (TheSelect->getOpcode() == ISD::SELECT) {
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// Check that the condition doesn't reach either load. If so, folding
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// this will induce a cycle into the DAG.
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if ((!LLD->hasAnyUseOfValue(1) ||
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!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
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(!RLD->hasAnyUseOfValue(1) ||
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!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
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Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
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LLD->getBasePtr().getValueType(),
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TheSelect->getOperand(0), LLD->getBasePtr(),
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RLD->getBasePtr());
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}
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} else {
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// Check that the condition doesn't reach either load. If so, folding
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// this will induce a cycle into the DAG.
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if ((!LLD->hasAnyUseOfValue(1) ||
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(!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
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!LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
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(!RLD->hasAnyUseOfValue(1) ||
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(!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
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!RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
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Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
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LLD->getBasePtr().getValueType(),
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TheSelect->getOperand(0),
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TheSelect->getOperand(1),
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LLD->getBasePtr(), RLD->getBasePtr(),
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TheSelect->getOperand(4));
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if (LLDAddrSpace == 0 && RLDAddrSpace == 0) {
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if (TheSelect->getOpcode() == ISD::SELECT) {
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// Check that the condition doesn't reach either load. If so, folding
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// this will induce a cycle into the DAG.
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if ((!LLD->hasAnyUseOfValue(1) ||
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!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) &&
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(!RLD->hasAnyUseOfValue(1) ||
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!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) {
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Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(),
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LLD->getBasePtr().getValueType(),
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TheSelect->getOperand(0), LLD->getBasePtr(),
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RLD->getBasePtr());
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}
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} else {
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// Check that the condition doesn't reach either load. If so, folding
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// this will induce a cycle into the DAG.
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if ((!LLD->hasAnyUseOfValue(1) ||
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(!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
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!LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) &&
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(!RLD->hasAnyUseOfValue(1) ||
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(!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) &&
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!RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) {
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Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(),
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LLD->getBasePtr().getValueType(),
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TheSelect->getOperand(0),
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TheSelect->getOperand(1),
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LLD->getBasePtr(), RLD->getBasePtr(),
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TheSelect->getOperand(4));
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}
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}
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}
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