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[SPARC] Recognize the prefetch instruction 

Reviewed By: LemonBoy

Differential Revision: https://reviews.llvm.org/D96311
This commit is contained in:
Joerg Sonnenberger 2021-10-20 10:36:27 +02:00 committed by Daniel Cederman
parent 862e8d7e55
commit ec428f7b78
2 changed files with 21 additions and 0 deletions
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11
llvm/lib/Target/Sparc/SparcInstrInfo.td
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@ -1623,6 +1623,17 @@ let hasSideEffects = 1 in {
}
}
// Section A.42 - Prefetch Data
let Predicates = [HasV9] in {
def PREFETCHr : F3_1<3, 0b101101,
(outs), (ins MEMrr:$addr, shift_imm5:$rd),
"prefetch [$addr], $rd", []>;
def PREFETCHi : F3_2<3, 0b101101,
(outs), (ins MEMri:$addr, shift_imm5:$rd),
"prefetch [$addr], $rd", []>;
}
// Section A.43 - Read Privileged Register Instructions
let Predicates = [HasV9] in {

10
llvm/test/MC/Sparc/sparcv9-instructions.s
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@ -301,3 +301,13 @@
! V9: st %o1, [%o0] ! encoding: [0xd2,0x22,0x00,0x00]
stw %o1, [%o0]
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: prefetch [ %i1 + 0xf80 ], 1
! V9: prefetch [%i1+3968], 1 ! encoding: [0xc3,0x6e,0x6f,0x80]
prefetch [ %i1 + 0xf80 ], 1
! V8: error: instruction requires a CPU feature not currently enabled
! V8-NEXT: prefetch [ %i1 + %i2 ], 1
! V9: prefetch [%i1+%i2], 1 ! encoding: [0xc3,0x6e,0x40,0x1a]
prefetch [ %i1 + %i2 ], 1