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[TwoAddressInstructionPass] Update existing physreg live intervals 

In TwoAddressInstructionPass::processTiedPairs with
-early-live-intervals, update any preexisting physreg live intervals,
as well as virtreg live intervals. By default (without
-precompute-phys-liveness) physreg live intervals only exist for
registers that are live-in to some basic block.

Differential Revision: https://reviews.llvm.org/D113191
This commit is contained in:
Jay Foad 2021-11-04 13:43:09 +00:00
parent 020ca1747d
commit ec0e1e88d2
4 changed files with 15 additions and 4 deletions
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16
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1539,15 +1539,23 @@ TwoAddressInstructionPass::processTiedPairs(MachineInstr *MI,
if (LIS) {
LastCopyIdx = LIS->InsertMachineInstrInMaps(*PrevMI).getRegSlot();
SlotIndex endIdx =
LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
if (RegA.isVirtual()) {
LiveInterval &LI = LIS->getInterval(RegA);
VNInfo *VNI = LI.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
SlotIndex endIdx =
LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
LI.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
for (auto &S : LI.subranges()) {
VNI = S.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
S.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
S.addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
}
} else {
for (MCRegUnitIterator Unit(RegA, TRI); Unit.isValid(); ++Unit) {
if (LiveRange *LR = LIS->getCachedRegUnit(*Unit)) {
VNInfo *VNI =
LR->getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
LR->addSegment(LiveRange::Segment(LastCopyIdx, endIdx, VNI));
}
}
}
}

1
llvm/test/CodeGen/ARM/inlineasm-operand-implicit-cast.ll
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@ -1,4 +1,5 @@
; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 < %s | FileCheck %s
; RUN: llc -mtriple armv7-arm-linux-gnueabihf -O2 -mcpu=cortex-a7 -early-live-intervals < %s | FileCheck %s
%struct.twofloat = type { float, float }
%struct.twodouble = type { double, double }

1
llvm/test/CodeGen/Thumb/emergency-spill-slot.ll
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@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s
; RUN: llc -early-live-intervals < %s | FileCheck %s
target triple = "thumbv6m-unknown-unknown-eabi"
define void @vla_emergency_spill(i32 %n) {

1
llvm/test/CodeGen/X86/inline-asm-A-constraint.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-- -early-live-intervals < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64--"