forked from OSchip/llvm-project
[NFC] Replace hard-coded usages of SystemZ::R15D with SpecialRegisters API
This patch changes hard-coded usages of SystemZ::R15D with calls to the getStackPointerRegister function. Uses in the LowerCall function are avoided to avoid merge conflicts with an expected upcoming patch. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D109702
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llvm/lib/Target/SystemZ
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@ -82,6 +82,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
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: TargetLowering(TM), Subtarget(STI) {
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MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0));
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auto *Regs = STI.getSpecialRegisters();
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// Set up the register classes.
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if (Subtarget.hasHighWord())
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addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
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@ -115,7 +117,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
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computeRegisterProperties(Subtarget.getRegisterInfo());
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// Set up special registers.
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setStackPointerRegisterToSaveRestore(SystemZ::R15D);
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setStackPointerRegisterToSaveRestore(Regs->getStackPointerRegister());
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// TODO: It may be better to default to latency-oriented scheduling, however
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// LLVM's current latency-oriented scheduler can't handle physreg definitions
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@ -4140,17 +4142,21 @@ SystemZTargetLowering::getTargetMMOFlags(const Instruction &I) const {
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SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
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SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
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auto *Regs = Subtarget->getSpecialRegisters();
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MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
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if (MF.getFunction().getCallingConv() == CallingConv::GHC)
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report_fatal_error("Variable-sized stack allocations are not supported "
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"in GHC calling convention");
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return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
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SystemZ::R15D, Op.getValueType());
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Regs->getStackPointerRegister(), Op.getValueType());
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}
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SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
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SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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const SystemZSubtarget *Subtarget = &MF.getSubtarget<SystemZSubtarget>();
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auto *Regs = Subtarget->getSpecialRegisters();
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MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
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bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain");
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@ -4164,12 +4170,13 @@ SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
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SDLoc DL(Op);
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if (StoreBackchain) {
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SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64);
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SDValue OldSP = DAG.getCopyFromReg(
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Chain, DL, Regs->getStackPointerRegister(), MVT::i64);
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Backchain = DAG.getLoad(MVT::i64, DL, Chain, getBackchainAddress(OldSP, DAG),
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MachinePointerInfo());
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}
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Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP);
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Chain = DAG.getCopyToReg(Chain, DL, Regs->getStackPointerRegister(), NewSP);
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if (StoreBackchain)
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Chain = DAG.getStore(Chain, DL, Backchain, getBackchainAddress(NewSP, DAG),
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