From ebe06910ce2623f525e458a91d7e5a1858163226 Mon Sep 17 00:00:00 2001 From: Anirudh Prasad Date: Fri, 24 Sep 2021 14:59:29 -0400 Subject: [PATCH] [NFC] Replace hard-coded usages of SystemZ::R15D with SpecialRegisters API This patch changes hard-coded usages of SystemZ::R15D with calls to the getStackPointerRegister function. Uses in the LowerCall function are avoided to avoid merge conflicts with an expected upcoming patch. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D109702 --- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index de760c278ef9..e65dfea15f0c 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -82,6 +82,8 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, : TargetLowering(TM), Subtarget(STI) { MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize(0)); + auto *Regs = STI.getSpecialRegisters(); + // Set up the register classes. if (Subtarget.hasHighWord()) addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass); @@ -115,7 +117,7 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, computeRegisterProperties(Subtarget.getRegisterInfo()); // Set up special registers. - setStackPointerRegisterToSaveRestore(SystemZ::R15D); + setStackPointerRegisterToSaveRestore(Regs->getStackPointerRegister()); // TODO: It may be better to default to latency-oriented scheduling, however // LLVM's current latency-oriented scheduler can't handle physreg definitions @@ -4140,17 +4142,21 @@ SystemZTargetLowering::getTargetMMOFlags(const Instruction &I) const { SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); + const SystemZSubtarget *Subtarget = &MF.getSubtarget(); + auto *Regs = Subtarget->getSpecialRegisters(); MF.getInfo()->setManipulatesSP(true); if (MF.getFunction().getCallingConv() == CallingConv::GHC) report_fatal_error("Variable-sized stack allocations are not supported " "in GHC calling convention"); return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op), - SystemZ::R15D, Op.getValueType()); + Regs->getStackPointerRegister(), Op.getValueType()); } SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const { MachineFunction &MF = DAG.getMachineFunction(); + const SystemZSubtarget *Subtarget = &MF.getSubtarget(); + auto *Regs = Subtarget->getSpecialRegisters(); MF.getInfo()->setManipulatesSP(true); bool StoreBackchain = MF.getFunction().hasFnAttribute("backchain"); @@ -4164,12 +4170,13 @@ SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op, SDLoc DL(Op); if (StoreBackchain) { - SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, MVT::i64); + SDValue OldSP = DAG.getCopyFromReg( + Chain, DL, Regs->getStackPointerRegister(), MVT::i64); Backchain = DAG.getLoad(MVT::i64, DL, Chain, getBackchainAddress(OldSP, DAG), MachinePointerInfo()); } - Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R15D, NewSP); + Chain = DAG.getCopyToReg(Chain, DL, Regs->getStackPointerRegister(), NewSP); if (StoreBackchain) Chain = DAG.getStore(Chain, DL, Backchain, getBackchainAddress(NewSP, DAG),