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[X86] Remove SLDT64m instruction. 

It doesn't really exist. The instruction always writes 16-bits of memory. Putting a REX.w on it won't change anything.

While I was touching the encoding tests to remove it, I added some other missing register form test cases.

llvm-svn: 331135
This commit is contained in:
Craig Topper 2018-04-29 04:50:53 +00:00
parent 8e3dbfd725
commit ebd3e4a69c
7 changed files with 11 additions and 30 deletions
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3
llvm/lib/Target/X86/X86InstrSystem.td
View File

@ -382,9 +382,6 @@ def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
// extension. // extension.
def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins), def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
"sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>; "sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
let mayStore = 1 in
def SLDT64m : RI<0x00, MRM0m, (outs), (ins i16mem:$dst),
"sldt{q}\t$dst", []>, TB, Requires<[In64BitMode]>;
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src), def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
"lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>; "lgdt{w}\t$src", []>, TB, OpSize16, Requires<[Not64BitMode]>;

1
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -455,7 +455,6 @@ def: InstRW<[BWWriteResGroup9], (instregex "LAHF", // TODO: This doesnt match Ag
"SAHF", // TODO: This doesn't match Agner's data "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m", "SGDT64m",
"SIDT64m", "SIDT64m",
"SLDT64m",
"SMSW16m", "SMSW16m",
"STRm", "STRm",
"SYSCALL")>; "SYSCALL")>;

1
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -786,7 +786,6 @@ def: InstRW<[HWWriteResGroup10], (instregex "CLC",
"NOOP", "NOOP",
"SGDT64m", "SGDT64m",
"SIDT64m", "SIDT64m",
"SLDT64m",
"SMSW16m", "SMSW16m",
"STC", "STC",
"STRm", "STRm",

1
llvm/lib/Target/X86/X86SchedSkylakeClient.td
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@ -539,7 +539,6 @@ def: InstRW<[SKLWriteResGroup10], (instregex "CLC",
"SAHF", // TODO: This doesn't match Agner's data "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m", "SGDT64m",
"SIDT64m", "SIDT64m",
"SLDT64m",
"SMSW16m", "SMSW16m",
"STC", "STC",
"STRm", "STRm",

1
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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@ -908,7 +908,6 @@ def: InstRW<[SKXWriteResGroup10], (instregex "CLC",
"SAHF", // TODO: This doesn't match Agner's data "SAHF", // TODO: This doesn't match Agner's data
"SGDT64m", "SGDT64m",
"SIDT64m", "SIDT64m",
"SLDT64m",
"SMSW16m", "SMSW16m",
"STC", "STC",
"STRm", "STRm",

4
llvm/test/MC/X86/I286-32.s
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@ -132,6 +132,10 @@ ltrw 64(%edx,%eax)
// CHECK: encoding: [0x0f,0x00,0x1a] // CHECK: encoding: [0x0f,0x00,0x1a]
ltrw (%edx) ltrw (%edx)
// CHECK: sldtw %ax
// CHECK: encoding: [0x66,0x0f,0x00,0xc0]
sldtw %ax
// CHECK: sldtl %eax // CHECK: sldtl %eax
// CHECK: encoding: [0x0f,0x00,0xc0] // CHECK: encoding: [0x0f,0x00,0xc0]
sldtl %eax sldtl %eax

30
llvm/test/MC/X86/I286-64.s
View File

@ -240,33 +240,17 @@ sidtq 64(%rdx,%rax)
// CHECK: encoding: [0x0f,0x01,0x0a] // CHECK: encoding: [0x0f,0x01,0x0a]
sidtq (%rdx) sidtq (%rdx)
// CHECK: sldtw %r13w
// CHECK: encoding: [0x66,0x41,0x0f,0x00,0xc5]
sldtw %r13w
// CHECK: sldtl %r13d // CHECK: sldtl %r13d
// CHECK: encoding: [0x41,0x0f,0x00,0xc5] // CHECK: encoding: [0x41,0x0f,0x00,0xc5]
sldtl %r13d sldtl %r13d
// CHECK: sldtq 485498096 // CHECK: sldtq %r13
// CHECK: encoding: [0x48,0x0f,0x00,0x04,0x25,0xf0,0x1c,0xf0,0x1c] // CHECK: encoding: [0x49,0x0f,0x00,0xc5]
sldtq 485498096 sldtq %r13
// CHECK: sldtq 64(%rdx)
// CHECK: encoding: [0x48,0x0f,0x00,0x42,0x40]
sldtq 64(%rdx)
// CHECK: sldtq 64(%rdx,%rax,4)
// CHECK: encoding: [0x48,0x0f,0x00,0x44,0x82,0x40]
sldtq 64(%rdx,%rax,4)
// CHECK: sldtq -64(%rdx,%rax,4)
// CHECK: encoding: [0x48,0x0f,0x00,0x44,0x82,0xc0]
sldtq -64(%rdx,%rax,4)
// CHECK: sldtq 64(%rdx,%rax)
// CHECK: encoding: [0x48,0x0f,0x00,0x44,0x02,0x40]
sldtq 64(%rdx,%rax)
// CHECK: sldtq (%rdx)
// CHECK: encoding: [0x48,0x0f,0x00,0x02]
sldtq (%rdx)
// CHECK: sldtw 485498096 // CHECK: sldtw 485498096
// CHECK: encoding: [0x0f,0x00,0x04,0x25,0xf0,0x1c,0xf0,0x1c] // CHECK: encoding: [0x0f,0x00,0x04,0x25,0xf0,0x1c,0xf0,0x1c]