diff --git a/lldb/include/lldb/Core/EmulateInstruction.h b/lldb/include/lldb/Core/EmulateInstruction.h index 274e708297f7..6e9ef9557619 100644 --- a/lldb/include/lldb/Core/EmulateInstruction.h +++ b/lldb/include/lldb/Core/EmulateInstruction.h @@ -139,6 +139,8 @@ public: eContextMultiplication, eContextAddition, + + eContextSubtraction, eContextReturnFromException }; diff --git a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp index 57b4075e09f8..ba153866482f 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp +++ b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp @@ -9171,6 +9171,689 @@ EmulateInstructionARM::EmulateTSTReg (const uint32_t opcode, const ARMEncoding e } return true; } + +// A8.6.216 SUB (SP minus register) +bool +EmulateInstructionARM::EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 + if ConditionPassed() then + EncodingSpecificOperations(); + shifted = Shift(R[m], shift_t, shift_n, APSR.C); + (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), ‘1’); + if d == 15 then // Can only occur for ARM encoding + ALUWritePC(result); // setflags is always FALSE here + else + R[d] = result; + if setflags then + APSR.N = result<31>; + APSR.Z = IsZeroBit(result); + APSR.C = carry; + APSR.V = overflow; +#endif + + bool success = false; + + if (ConditionPassed(opcode)) + { + uint32_t d; + uint32_t m; + bool setflags; + ARM_ShifterType shift_t; + uint32_t shift_n; + + switch (encoding) + { + case eEncodingT1: + // d = UInt(Rd); m = UInt(Rm); setflags = (S == ‘1’); + d = Bits32 (opcode, 11, 8); + m = Bits32 (opcode, 3, 0); + setflags = BitIsSet (opcode, 20); + + // (shift_t, shift_n) = DecodeImmShift(type, imm3:imm2); + shift_n = DecodeImmShiftThumb (opcode, shift_t); + + // if d == 13 && (shift_t != SRType_LSL || shift_n > 3) then UNPREDICTABLE; + if ((d == 13) && ((shift_t != SRType_LSL) || (shift_n > 3))) + return false; + + // if d == 15 || BadReg(m) then UNPREDICTABLE; + if ((d == 15) || BadReg (m)) + return false; + break; + + case eEncodingA1: + // if Rd == ‘1111’ && S == ‘1’ then SEE SUBS PC, LR and related instructions; + // d = UInt(Rd); m = UInt(Rm); setflags = (S == ‘1’); + d = Bits32 (opcode, 15, 12); + m = Bits32 (opcode, 3, 0); + setflags = BitIsSet (opcode, 20); + + // (shift_t, shift_n) = DecodeImmShift(type, imm5); + shift_n = DecodeImmShiftARM (opcode, shift_t); + break; + + default: + return false; + } + + // shifted = Shift(R[m], shift_t, shift_n, APSR.C); + uint32_t Rm = ReadCoreReg (m, &success); + if (!success) + return false; + + uint32_t shifted = Shift (Rm, shift_t, shift_n, APSR_C); + + // (result, carry, overflow) = AddWithCarry(SP, NOT(shifted), ‘1’); + uint32_t sp_val = ReadCoreReg (SP_REG, &success); + if (!success) + return false; + + AddWithCarryResult res = AddWithCarry (sp_val, ~shifted, 1); + + EmulateInstruction::Context context; + context.type = eContextSubtraction; + Register sp_reg; + sp_reg.SetRegister (eRegisterKindDWARF, dwarf_sp); + Register dwarf_reg; + dwarf_reg.SetRegister (eRegisterKindDWARF, dwarf_r0 + m); + context.SetRegisterRegisterOperands (sp_reg, dwarf_reg); + + uint32_t regnum = dwarf_r0 + d; + + if (!WriteCoreRegOptionalFlags(context, res.result, regnum, setflags, res.carry_out, res.overflow)) + return false; + } + return true; +} + + +// A8.6.7 ADD (register-shifted register) +bool +EmulateInstructionARM::EmulateAddRegShift (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.213 SUB (register) +bool +EmulateInstructionARM::EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.202 STREX +bool +EmulateInstructionARM::EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.197 STRB (immediate, ARM) +bool +EmulateInstructionARM::EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.194 STR (immediate, ARM) +bool +EmulateInstructionARM::EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.74 LDRH (immediate, ARM) +bool +EmulateInstructionARM::EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.69 LDREX +bool +EmulateInstructionARM::EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.62 LDRB (immediate, ARM) +bool +EmulateInstructionARM::EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + +// A8.6.59 LDR (literal) +bool +EmulateInstructionARM::EmulateLDRLiteral (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.65 LDRBT +bool +EmulateInstructionARM::EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.66 LDRD (immediate) +bool +EmulateInstructionARM::EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.67 LDRD (literal) +bool +EmulateInstructionARM::EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.68 LDRD (register) +bool +EmulateInstructionARM::EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.70 LDREXB +bool +EmulateInstructionARM::EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.71 LDREXD +bool +EmulateInstructionARM::EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.72 LDREXH +bool +EmulateInstructionARM::EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.77 LDRHT +bool +EmulateInstructionARM::EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.81 LDRSBT +bool +EmulateInstructionARM::EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.85 LDRSHT +bool +EmulateInstructionARM::EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.86 LDRT +bool +EmulateInstructionARM::EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.198 STRB (register) +bool +EmulateInstructionARM::EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.199 STRBT +bool +EmulateInstructionARM::EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.200 STRD (immediate) +bool +EmulateInstructionARM::EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.201 STRD (register) +bool +EmulateInstructionARM::EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.203 STREXB +bool +EmulateInstructionARM::EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.204 STREXD +bool +EmulateInstructionARM::EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.205 STREXH +bool +EmulateInstructionARM::EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.206 STRH (immediate, Thumb) +bool +EmulateInstructionARM::EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.207 STRH (immediate, ARM) +bool +EmulateInstructionARM::EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + +// A8.6.209 STRHT +bool +EmulateInstructionARM::EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + //bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + +// A8.6.210 STRT +bool +EmulateInstructionARM::EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding) +{ +#if 0 +#endif + + // bool success = false; + + if (ConditionPassed(opcode)) + { + switch (encoding) + { + } + } + return true; +} + + + EmulateInstructionARM::ARMOpcode* EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) @@ -9196,6 +9879,7 @@ EmulateInstructionARM::GetARMOpcodeForInstruction (const uint32_t opcode) // adjust the stack pointer { 0x0ffff000, 0x024dd000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #"}, + { 0x0fef0010, 0x004d0000, ARMvAll, eEncodingA1, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s} , sp, {,}" }, // push one register // if Rn == '1101' && imm12 == '000000000100' then SEE PUSH; @@ -9407,6 +10091,7 @@ EmulateInstructionARM::GetThumbOpcodeForInstruction (const uint32_t opcode) { 0xffffff80, 0x0000b080, ARMvAll, eEncodingT1, eSize16, &EmulateInstructionARM::EmulateSUBSPImm, "sub sp, sp, #imm"}, { 0xfbef8f00, 0xf1ad0d00, ARMV6T2_ABOVE, eEncodingT2, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "sub.w sp, sp, #"}, { 0xfbff8f00, 0xf2ad0d00, ARMV6T2_ABOVE, eEncodingT3, eSize32, &EmulateInstructionARM::EmulateSUBSPImm, "subw sp, sp, #imm12"}, + { 0xffef8000, 0xebad0000, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateSUBSPReg, "sub{s} , sp, {,}" }, // vector push consecutive extension register(s) { 0xffbf0f00, 0xed2d0b00, ARMV6T2_ABOVE, eEncodingT1, eSize32, &EmulateInstructionARM::EmulateVPUSH, "vpush.64 "}, diff --git a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h index d6e05dc4f807..e49d93e1db8f 100644 --- a/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h +++ b/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.h @@ -371,6 +371,10 @@ protected: // A8.6.215 SUB (SP minus immediate) bool EmulateSUBSPImm (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.216 SUB (SP minus register) + bool + EmulateSUBSPReg (const uint32_t opcode, const ARMEncoding encoding); // A8.6.194 STR (immediate, ARM) -- Rn == sp bool @@ -415,6 +419,10 @@ protected: // A8.6.6 ADD (register) bool EmulateADDReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.7 ADD (register-shifted register) + bool + EmulateAddRegShift (const uint32_t opcode, const ARMEncoding encoding); // A8.6.97 MOV (register) bool @@ -476,6 +484,8 @@ protected: bool EmulateShiftReg (const uint32_t opcode, const ARMEncoding encoding, ARM_ShifterType shift_type); + // LOAD FUNCTIONS + // A8.6.53 LDM/LDMIA/LDMFD bool EmulateLDM (const uint32_t opcode, const ARMEncoding encoding); @@ -496,37 +506,212 @@ protected: bool EmulateLDRRtRnImm (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.188 STM/STMIA/STMEA + // A8.6.58 LDR (immediate, ARM) - Encoding A1 + bool + EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.59 LDR (literal) + bool + EmulateLDRLiteral (const uint32_t, const ARMEncoding encoding); + + // A8.6.60 LDR (register) - Encoding T1, T2, A1 + bool + EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2, T3 + bool + EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.62 LDRB (immediate, ARM) + bool + EmulateLDRBImmediateARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.63 LDRB (literal) - Encoding T1, A1 + bool + EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.64 LDRB (register) - Encoding T1, T2, A1 + bool + EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.65 LDRBT + bool + EmulateLDRBT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.66 LDRD (immediate) + bool + EmulateLDRDImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.67 + bool + EmulateLDRDLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.68 LDRD (register) + bool + EmulateLDRDRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.69 LDREX + bool + EmulateLDREX (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.70 LDREXB + bool + EmulateLDREXB (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.71 LDREXD + bool + EmulateLDREXD (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.72 LDREXH + bool + EmulateLDREXH (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2, T3 + bool + EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.74 LDRS (immediate, ARM) + bool + EmulateLDRHImmediateARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.75 LDRH (literal) - Encoding T1, A1 + bool + EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.76 LDRH (register) - Encoding T1, T2, A1 + bool + EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.77 LDRHT + bool + EmulateLDRHT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.78 LDRSB (immediate) - Encoding T1, T2, A1 + bool + EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.79 LDRSB (literal) - Encoding T1, A1 + bool + EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.80 LDRSB (register) - Encoding T1, T2, A1 + bool + EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.81 LDRSBT + bool + EmulateLDRSBT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.82 LDRSH (immediate) - Encoding T1, T2, A1 + bool + EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.83 LDRSH (literal) - Encoding T1, A1 + bool + EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.84 LDRSH (register) - Encoding T1, T2, A1 + bool + EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.85 LDRSHT + bool + EmulateLDRSHT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.86 + bool + EmulateLDRT (const uint32_t opcode, const ARMEncoding encoding); + + + // STORE FUNCTIONS + + // A8.6.189 STM/STMIA/STMEA bool EmulateSTM (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.189 STMDA/STMED + // A8.6.190 STMDA/STMED bool EmulateSTMDA (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.190 STMDB/STMFD + // A8.6.191 STMDB/STMFD bool EmulateSTMDB (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.191 STMIB/STMFA + // A8.6.192 STMIB/STMFA bool EmulateSTMIB (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.192 STR (immediate, Thumb) + // A8.6.193 STR (immediate, Thumb) bool EmulateSTRThumb(const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.194 STR (immediate, ARM) + bool + EmulateSTRImmARM (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.194 STR (register) + // A8.6.195 STR (register) bool EmulateSTRRegister (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.195 STRB (immediate, Thumb) + // A8.6.196 STRB (immediate, Thumb) bool EmulateSTRBThumb (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.207 STRH (register) + + // A8.6.197 STRB (immediate, ARM) + bool + EmulateSTRBImmARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.198 STRB (register) + bool + EmulateSTRBReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.199 STRBT + bool + EmulateSTRBT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.200 STRD (immediate) + bool + EmulateSTRDImm (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.201 STRD (register) + bool + EmulateSTRDReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.202 STREX + bool + EmulateSTREX (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.203 STREXB + bool + EmulateSTREXB (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.204 STREXD + bool + EmulateSTREXD (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.205 STREXH + bool + EmulateSTREXH (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.206 STRH (immediate, Thumb) + bool + EmulateSTRHImmThumb (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.207 STRH (immediate, ARM) + bool + EmulateSTRHImmARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.208 STRH (register) bool EmulateSTRHRegister (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.209 STRHT + bool + EmulateSTRHT (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.210 STRT + bool + EmulateSTRT (const uint32_t opcode, const ARMEncoding encoding); // A8.6.1 ADC (immediate) bool @@ -576,62 +761,6 @@ protected: bool EmulateEORReg (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.58 LDR (immediate, ARM) - Encoding A1 - bool - EmulateLDRImmediateARM (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.60 LDR (register) - Encoding T1, T2, A1 - bool - EmulateLDRRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.61 LDRB (immediate, Thumb) - Encoding T1, T2 - bool - EmulateLDRBImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.63 LDRB (literal) - Encoding T1 - bool - EmulateLDRBLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.64 LDRB (register) - Encoding T1 - bool - EmulateLDRBRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.73 LDRH (immediate, Thumb) - Encoding T1, T2 - bool - EmulateLDRHImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.75 LDRH (literal) - Encoding T1 - bool - EmulateLDRHLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.76 LDRH (register) - Encoding T1, T2 - bool - EmulateLDRHRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.78 LDRSB (immediate) - Encoding T1 - bool - EmulateLDRSBImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.79 LDRSB (literal) - Encoding T1 - bool - EmulateLDRSBLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.80 LDRSB (register) - Encoding T1, T2 - bool - EmulateLDRSBRegister (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.82 LDRSH (immediate) - Encoding T1 - bool - EmulateLDRSHImmediate (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.83 LDRSH (literal) - Encoding T1 - bool - EmulateLDRSHLiteral (const uint32_t opcode, const ARMEncoding encoding); - - // A8.6.84 LDRSH (register) - Encoding T1, T2 - bool - EmulateLDRSHRegister (const uint32_t opcode, const ARMEncoding encoding); - // A8.6.105 MUL bool EmulateMUL (const uint32_t opcode, const ARMEncoding encoding); @@ -695,6 +824,14 @@ protected: // A8.6.212 SUB (immediate, ARM) bool EmulateSUBImmARM (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.213 SUB (register) + bool + EmulateSUBReg (const uint32_t opcode, const ARMEncoding encoding); + + // A8.6.214 SUB (register-shifted register) + bool + EmulateSUBRegShift (const uint32_t opcode, const ARMEncoding encoding); // A8.6.222 SXTB - Encoding T1 bool