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AMDGPU/GlobalISel: Mark 32-bit G_SHL as legal 

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D34589

llvm-svn: 306298
This commit is contained in:
Tom Stellard 2017-06-26 15:56:52 +00:00
parent 33eb775265
commit eb8f1e27d9
2 changed files with 20 additions and 0 deletions
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2
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
View File

@ -69,6 +69,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
setAction({G_SELECT, S32}, Legal);
setAction({G_SELECT, 1, S1}, Legal);
setAction({G_SHL, S32}, Legal);
setAction({G_STORE, S32}, Legal);
setAction({G_STORE, 1, P1}, Legal);

18
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir Normal file
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@ -0,0 +1,18 @@
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: test_shl
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0.entry:
liveins: %vgpr0, %vgpr1
; CHECK-LABEL: name: test_shl
; CHECK: %2(s32) = G_SHL %0, %1
%0(s32) = COPY %vgpr0
%1(s32) = COPY %vgpr1
%2(s32) = G_SHL %0, %1
...