forked from OSchip/llvm-project
[AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.
This patch adds parsing support for 'vector + shift/extend' and corresponding asm operand classes, needed for implementing SVE's gather/scatter addressing modes. The added combinations of vector (ZPR) and Shift/Extend are: Unscaled: ZPR64ExtLSL8: signed 64-bit offsets (z0.d) ZPR32ExtUXTW8: unsigned 32-bit offsets (z0.s, uxtw) ZPR32ExtSXTW8: signed 32-bit offsets (z0.s, sxtw) Unpacked and unscaled: ZPR64ExtUXTW8: unsigned 32-bit offsets (z0.d, uxtw) ZPR64ExtSXTW8: signed 32-bit offsets (z0.d, sxtw) Unpacked and scaled: ZPR64ExtUXTW<scale>: unsigned 32-bit offsets (z0.d, uxtw #<shift>) ZPR64ExtSXTW<scale>: signed 32-bit offsets (z0.d, sxtw #<shift>) Scaled: ZPR32ExtUXTW<scale>: unsigned 32-bit offsets (z0.s, uxtw #<shift>) ZPR32ExtSXTW<scale>: signed 32-bit offsets (z0.s, sxtw #<shift>) ZPR64ExtLSL<scale>: unsigned 64-bit offsets (z0.d, lsl #<shift>) ZPR64ExtLSL<scale>: signed 64-bit offsets (z0.d, lsl #<shift>) Patch [1/3] in series to add support for SVE's gather load instructions that use scalar+vector addressing modes: - Patch [1/3]: https://reviews.llvm.org/D45951 - Patch [2/3]: https://reviews.llvm.org/D46023 - Patch [3/3]: https://reviews.llvm.org/D45958 Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar Reviewed By: fhahn Differential Revision: https://reviews.llvm.org/D45951 llvm-svn: 330805
This commit is contained in:
Sander de Smalen
parent
bec2a7c4eb
commit
eb896b148b
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@ -821,7 +821,7 @@ class ZPRAsmOperand <string name, int Width>: AsmOperandClass {
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let PredicateMethod = "isSVEVectorRegOfWidth<"
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# Width # ", AArch64::ZPRRegClassID>";
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let RenderMethod = "addRegOperands";
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let ParserMethod = "tryParseSVEDataVector<"
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let ParserMethod = "tryParseSVEDataVector<false, "
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# !if(!eq(Width, 0), "false", "true") # ">";
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}
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@ -934,6 +934,64 @@ def ZZZZ_d : RegisterOperand<ZPR4, "printTypedVectorList<0,'d'>"> {
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let ParserMatchClass = ZPRVectorList<64, 4>;
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}
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class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale>
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: AsmOperandClass {
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let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale;
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let PredicateMethod = "isSVEVectorRegWithShiftExtend<"
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# RegWidth # ", AArch64::ZPRRegClassID, "
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# "AArch64_AM::" # ShiftExtend # ", "
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# Scale # ">";
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let DiagnosticType = "InvalidZPR" # RegWidth # ShiftExtend # Scale;
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let RenderMethod = "addRegOperands";
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let ParserMethod = "tryParseSVEDataVector<true, true>";
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}
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class ZPRExtendRegisterOperand<bit SignExtend, bit IsLSL, string Repr,
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int RegWidth, int Scale> : RegisterOperand<ZPR> {
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let ParserMatchClass =
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!cast<AsmOperandClass>("ZPR" # RegWidth # "AsmOpndExt" # Repr # Scale);
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let PrintMethod = "printRegWithShiftExtend<"
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# !if(SignExtend, "true", "false") # ", "
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# Scale # ", "
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# !if(IsLSL, "'x'", "'w'") # ", "
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# !if(!eq(RegWidth, 32), "'s'", "'d'") # ">";
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}
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foreach RegWidth = [32, 64] in {
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// UXTW(8|16|32|64)
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def ZPR#RegWidth#AsmOpndExtUXTW8 : ZPRExtendAsmOperand<"UXTW", RegWidth, 8>;
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def ZPR#RegWidth#AsmOpndExtUXTW16 : ZPRExtendAsmOperand<"UXTW", RegWidth, 16>;
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def ZPR#RegWidth#AsmOpndExtUXTW32 : ZPRExtendAsmOperand<"UXTW", RegWidth, 32>;
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def ZPR#RegWidth#AsmOpndExtUXTW64 : ZPRExtendAsmOperand<"UXTW", RegWidth, 64>;
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def ZPR#RegWidth#ExtUXTW8 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 8>;
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def ZPR#RegWidth#ExtUXTW16 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 16>;
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def ZPR#RegWidth#ExtUXTW32 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 32>;
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def ZPR#RegWidth#ExtUXTW64 : ZPRExtendRegisterOperand<0b0, 0b0, "UXTW", RegWidth, 64>;
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// SXTW(8|16|32|64)
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def ZPR#RegWidth#AsmOpndExtSXTW8 : ZPRExtendAsmOperand<"SXTW", RegWidth, 8>;
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def ZPR#RegWidth#AsmOpndExtSXTW16 : ZPRExtendAsmOperand<"SXTW", RegWidth, 16>;
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def ZPR#RegWidth#AsmOpndExtSXTW32 : ZPRExtendAsmOperand<"SXTW", RegWidth, 32>;
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def ZPR#RegWidth#AsmOpndExtSXTW64 : ZPRExtendAsmOperand<"SXTW", RegWidth, 64>;
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def ZPR#RegWidth#ExtSXTW8 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 8>;
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def ZPR#RegWidth#ExtSXTW16 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 16>;
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def ZPR#RegWidth#ExtSXTW32 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 32>;
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def ZPR#RegWidth#ExtSXTW64 : ZPRExtendRegisterOperand<0b1, 0b0, "SXTW", RegWidth, 64>;
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}
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// LSL(8|16|32|64)
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def ZPR64AsmOpndExtLSL8 : ZPRExtendAsmOperand<"LSL", 64, 8>;
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def ZPR64AsmOpndExtLSL16 : ZPRExtendAsmOperand<"LSL", 64, 16>;
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def ZPR64AsmOpndExtLSL32 : ZPRExtendAsmOperand<"LSL", 64, 32>;
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def ZPR64AsmOpndExtLSL64 : ZPRExtendAsmOperand<"LSL", 64, 64>;
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def ZPR64ExtLSL8 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 8>;
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def ZPR64ExtLSL16 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 16>;
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def ZPR64ExtLSL32 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 32>;
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def ZPR64ExtLSL64 : ZPRExtendRegisterOperand<0b0, 0b1, "LSL", 64, 64>;
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class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegClass> : AsmOperandClass {
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let Name = AsmOperandName # Scale;
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let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
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@ -944,7 +1002,7 @@ class GPR64ShiftExtendAsmOperand <string AsmOperandName, int Scale, string RegCl
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class GPR64ExtendRegisterOperand<string Name, int Scale, RegisterClass RegClass> : RegisterOperand<RegClass>{
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let ParserMatchClass = !cast<AsmOperandClass>(Name);
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let PrintMethod = "printRegWithShiftExtend<false, " # Scale # ", 'x'>";
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let PrintMethod = "printRegWithShiftExtend<false, " # Scale # ", 'x', 0>";
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}
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foreach Scale = [8, 16, 32, 64] in {
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@ -140,7 +140,7 @@ private:
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OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
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template <bool ParseShiftExtend>
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OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
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template <bool ParseSuffix>
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template <bool ParseShiftExtend, bool ParseSuffix>
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OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
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OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
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template <RegKind VectorKind>
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@ -857,6 +857,14 @@ public:
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(ElementWidth == 0 || Reg.ElementWidth == ElementWidth);
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}
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template <int ElementWidth, unsigned Class,
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AArch64_AM::ShiftExtendType ShiftExtendTy, int ShiftWidth>
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bool isSVEVectorRegWithShiftExtend() const {
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return Kind == k_Register && isSVEVectorRegOfWidth<ElementWidth, Class>() &&
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ShiftExtendTy == getShiftExtendType() &&
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getShiftExtendAmount() == Log2_32(ShiftWidth / 8);
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}
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bool isGPR32as64() const {
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return Kind == k_Register && Reg.Kind == RegKind::Scalar &&
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AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(Reg.RegNum);
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@ -3839,6 +3847,38 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
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return Error(Loc, "register must be x0..x30 with required shift 'lsl #2'");
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case Match_InvalidGPR64NoXZRshifted64:
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return Error(Loc, "register must be x0..x30 with required shift 'lsl #3'");
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case Match_InvalidZPR32UXTW8:
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case Match_InvalidZPR32SXTW8:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw)'");
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case Match_InvalidZPR32UXTW16:
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case Match_InvalidZPR32SXTW16:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #1'");
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case Match_InvalidZPR32UXTW32:
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case Match_InvalidZPR32SXTW32:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #2'");
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case Match_InvalidZPR32UXTW64:
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case Match_InvalidZPR32SXTW64:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].s, (uxtw|sxtw) #3'");
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case Match_InvalidZPR64UXTW8:
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case Match_InvalidZPR64SXTW8:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, (uxtw|sxtw)'");
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case Match_InvalidZPR64UXTW16:
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case Match_InvalidZPR64SXTW16:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #1'");
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case Match_InvalidZPR64UXTW32:
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case Match_InvalidZPR64SXTW32:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #2'");
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case Match_InvalidZPR64UXTW64:
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case Match_InvalidZPR64SXTW64:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, (lsl|uxtw|sxtw) #3'");
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case Match_InvalidZPR64LSL8:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d'");
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case Match_InvalidZPR64LSL16:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #1'");
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case Match_InvalidZPR64LSL32:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #2'");
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case Match_InvalidZPR64LSL64:
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return Error(Loc, "invalid shift/extend specified, expected 'z[0..31].d, lsl #3'");
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case Match_InvalidSVEPattern:
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return Error(Loc, "invalid predicate pattern");
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case Match_InvalidSVEPredicateAnyReg:
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@ -4292,6 +4332,26 @@ bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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case Match_InvalidGPR64NoXZRshifted16:
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case Match_InvalidGPR64NoXZRshifted32:
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case Match_InvalidGPR64NoXZRshifted64:
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case Match_InvalidZPR32UXTW8:
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case Match_InvalidZPR32UXTW16:
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case Match_InvalidZPR32UXTW32:
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case Match_InvalidZPR32UXTW64:
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case Match_InvalidZPR32SXTW8:
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case Match_InvalidZPR32SXTW16:
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case Match_InvalidZPR32SXTW32:
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case Match_InvalidZPR32SXTW64:
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case Match_InvalidZPR64UXTW8:
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case Match_InvalidZPR64SXTW8:
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case Match_InvalidZPR64UXTW16:
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case Match_InvalidZPR64SXTW16:
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case Match_InvalidZPR64UXTW32:
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case Match_InvalidZPR64SXTW32:
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case Match_InvalidZPR64UXTW64:
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case Match_InvalidZPR64SXTW64:
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case Match_InvalidZPR64LSL8:
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case Match_InvalidZPR64LSL16:
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case Match_InvalidZPR64LSL32:
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case Match_InvalidZPR64LSL64:
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case Match_InvalidSVEPredicateAnyReg:
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case Match_InvalidSVEPattern:
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case Match_InvalidSVEPredicateBReg:
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@ -4897,7 +4957,7 @@ AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
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return MatchOperand_Success;
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}
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template <bool ParseSuffix>
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template <bool ParseShiftExtend, bool ParseSuffix>
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OperandMatchResultTy
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AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
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const SMLoc S = getLoc();
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@ -4919,9 +4979,29 @@ AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
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return MatchOperand_NoMatch;
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unsigned ElementWidth = KindRes->second;
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// No shift/extend is the default.
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if (!ParseShiftExtend || getParser().getTok().isNot(AsmToken::Comma)) {
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Operands.push_back(AArch64Operand::CreateVectorReg(
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RegNum, RegKind::SVEDataVector, ElementWidth, S, S, getContext()));
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return MatchOperand_Success;
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}
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// Eat the comma
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getParser().Lex();
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// Match the shift
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SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
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Res = tryParseOptionalShiftExtend(ExtOpnd);
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if (Res != MatchOperand_Success)
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return Res;
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auto Ext = static_cast<AArch64Operand *>(ExtOpnd.back().get());
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Operands.push_back(AArch64Operand::CreateVectorReg(
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RegNum, RegKind::SVEDataVector, ElementWidth, S, S,
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getContext()));
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RegNum, RegKind::SVEDataVector, ElementWidth, S, Ext->getEndLoc(),
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getContext(), Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
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Ext->hasShiftExtendAmount()));
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return MatchOperand_Success;
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}
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@ -991,12 +991,16 @@ void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
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printMemExtendImpl(SignExtend, DoShift, Width, SrcRegKind, O);
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}
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template <bool SignExtend, int ExtWidth, char SrcRegKind>
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template <bool SignExtend, int ExtWidth, char SrcRegKind, char Suffix>
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void AArch64InstPrinter::printRegWithShiftExtend(const MCInst *MI,
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unsigned OpNum,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printOperand(MI, OpNum, STI, O);
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if (Suffix == 's' || Suffix == 'd')
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O << '.' << Suffix;
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else
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assert(Suffix == 0 && "Unsupported suffix size");
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bool DoShift = ExtWidth != 8;
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if (SignExtend || DoShift || SrcRegKind == 'w') {
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@ -90,7 +90,7 @@ protected:
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const MCSubtargetInfo &STI, raw_ostream &O) {
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printMemExtend(MI, OpNum, O, SrcRegKind, Width);
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}
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template <bool SignedExtend, int ExtWidth, char SrcRegKind>
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template <bool SignedExtend, int ExtWidth, char SrcRegKind, char Suffix>
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void printRegWithShiftExtend(const MCInst *MI, unsigned OpNum,
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const MCSubtargetInfo &STI, raw_ostream &O);
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void printCondCode(const MCInst *MI, unsigned OpNum,
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