forked from OSchip/llvm-project
CodeGen: Use Register
This commit is contained in:
Matt Arsenault
parent
c8c987d310
commit
eb7f74e300
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@ -42,9 +42,9 @@ class APFloat;
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/// create a new virtual register in the correct class.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainRegToClass(MachineRegisterInfo &MRI,
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Register constrainRegToClass(MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI, unsigned Reg,
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const RegisterBankInfo &RBI, Register Reg,
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const TargetRegisterClass &RegClass);
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/// Constrain the Register operand OpIdx, so that it is now constrained to the
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@ -54,7 +54,7 @@ unsigned constrainRegToClass(MachineRegisterInfo &MRI,
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/// definition. The debug location of \p InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainOperandRegClass(const MachineFunction &MF,
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Register constrainOperandRegClass(const MachineFunction &MF,
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const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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@ -72,7 +72,7 @@ unsigned constrainOperandRegClass(const MachineFunction &MF,
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/// InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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unsigned constrainOperandRegClass(const MachineFunction &MF,
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Register constrainOperandRegClass(const MachineFunction &MF,
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const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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@ -110,13 +110,13 @@ void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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/// If \p VReg is defined by a G_CONSTANT fits in int64_t
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/// returns it.
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Optional<int64_t> getConstantVRegVal(unsigned VReg,
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Optional<int64_t> getConstantVRegVal(Register VReg,
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const MachineRegisterInfo &MRI);
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/// Simple struct used to hold a constant integer value and a virtual
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/// register.
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struct ValueAndVReg {
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int64_t Value;
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unsigned VReg;
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Register VReg;
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};
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/// If \p VReg is defined by a statically evaluable chain of
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/// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true)
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@ -126,10 +126,10 @@ struct ValueAndVReg {
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/// getConstantVRegVal.
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/// When \p HandleFConstants == false the function bails on G_FCONSTANTs.
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Optional<ValueAndVReg>
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getConstantVRegValWithLookThrough(unsigned VReg, const MachineRegisterInfo &MRI,
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getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
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bool LookThroughInstrs = true,
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bool HandleFConstants = true);
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const ConstantFP* getConstantFPVRegVal(unsigned VReg,
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const ConstantFP* getConstantFPVRegVal(Register VReg,
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const MachineRegisterInfo &MRI);
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/// See if Reg is defined by an single def instruction that is
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@ -114,7 +114,7 @@ private:
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/// MachineRegisterInfo callback to notify when new virtual
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/// registers are created.
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void MRI_NoteNewVirtualRegister(unsigned VReg) override;
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void MRI_NoteNewVirtualRegister(Register VReg) override;
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/// Check if MachineOperand \p MO is a last use/kill either in the
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/// main live range of \p LI or in one of the matching subregister ranges.
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@ -57,7 +57,7 @@ public:
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public:
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virtual ~Delegate() = default;
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virtual void MRI_NoteNewVirtualRegister(unsigned Reg) = 0;
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virtual void MRI_NoteNewVirtualRegister(Register Reg) = 0;
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};
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private:
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@ -143,7 +143,7 @@ private:
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/// Live in values are typically arguments in registers. LiveIn values are
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/// allowed to have virtual registers associated with them, stored in the
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/// second element.
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std::vector<std::pair<unsigned, unsigned>> LiveIns;
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std::vector<std::pair<MCRegister, Register>> LiveIns;
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public:
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explicit MachineRegisterInfo(MachineFunction *MF);
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@ -253,7 +253,7 @@ public:
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void moveOperands(MachineOperand *Dst, MachineOperand *Src, unsigned NumOps);
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/// Verify the sanity of the use list for Reg.
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void verifyUseList(unsigned Reg) const;
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void verifyUseList(Register Reg) const;
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/// Verify the use list of all registers.
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void verifyUseLists() const;
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@ -278,12 +278,12 @@ public:
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/// register.
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using reg_iterator =
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defusechain_iterator<true, true, false, true, false, false>;
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reg_iterator reg_begin(unsigned RegNo) const {
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reg_iterator reg_begin(Register RegNo) const {
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return reg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_iterator reg_end() { return reg_iterator(nullptr); }
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inline iterator_range<reg_iterator> reg_operands(unsigned Reg) const {
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inline iterator_range<reg_iterator> reg_operands(Register Reg) const {
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return make_range(reg_begin(Reg), reg_end());
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}
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@ -291,7 +291,7 @@ public:
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/// of the specified register, stepping by MachineInstr.
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using reg_instr_iterator =
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defusechain_instr_iterator<true, true, false, false, true, false>;
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reg_instr_iterator reg_instr_begin(unsigned RegNo) const {
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reg_instr_iterator reg_instr_begin(Register RegNo) const {
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return reg_instr_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_instr_iterator reg_instr_end() {
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@ -299,7 +299,7 @@ public:
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}
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inline iterator_range<reg_instr_iterator>
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reg_instructions(unsigned Reg) const {
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reg_instructions(Register Reg) const {
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return make_range(reg_instr_begin(Reg), reg_instr_end());
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}
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@ -307,20 +307,20 @@ public:
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/// of the specified register, stepping by bundle.
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using reg_bundle_iterator =
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defusechain_instr_iterator<true, true, false, false, false, true>;
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reg_bundle_iterator reg_bundle_begin(unsigned RegNo) const {
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reg_bundle_iterator reg_bundle_begin(Register RegNo) const {
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return reg_bundle_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_bundle_iterator reg_bundle_end() {
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return reg_bundle_iterator(nullptr);
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}
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inline iterator_range<reg_bundle_iterator> reg_bundles(unsigned Reg) const {
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inline iterator_range<reg_bundle_iterator> reg_bundles(Register Reg) const {
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return make_range(reg_bundle_begin(Reg), reg_bundle_end());
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}
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/// reg_empty - Return true if there are no instructions using or defining the
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/// specified register (it may be live-in).
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bool reg_empty(unsigned RegNo) const { return reg_begin(RegNo) == reg_end(); }
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bool reg_empty(Register RegNo) const { return reg_begin(RegNo) == reg_end(); }
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/// reg_nodbg_iterator/reg_nodbg_begin/reg_nodbg_end - Walk all defs and uses
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/// of the specified register, skipping those marked as Debug.
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@ -334,7 +334,7 @@ public:
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}
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inline iterator_range<reg_nodbg_iterator>
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reg_nodbg_operands(unsigned Reg) const {
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reg_nodbg_operands(Register Reg) const {
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return make_range(reg_nodbg_begin(Reg), reg_nodbg_end());
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}
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@ -343,7 +343,7 @@ public:
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/// skipping those marked as Debug.
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using reg_instr_nodbg_iterator =
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defusechain_instr_iterator<true, true, true, false, true, false>;
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reg_instr_nodbg_iterator reg_instr_nodbg_begin(unsigned RegNo) const {
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reg_instr_nodbg_iterator reg_instr_nodbg_begin(Register RegNo) const {
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return reg_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_instr_nodbg_iterator reg_instr_nodbg_end() {
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@ -351,7 +351,7 @@ public:
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}
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inline iterator_range<reg_instr_nodbg_iterator>
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reg_nodbg_instructions(unsigned Reg) const {
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reg_nodbg_instructions(Register Reg) const {
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return make_range(reg_instr_nodbg_begin(Reg), reg_instr_nodbg_end());
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}
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@ -360,7 +360,7 @@ public:
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/// skipping those marked as Debug.
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using reg_bundle_nodbg_iterator =
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defusechain_instr_iterator<true, true, true, false, false, true>;
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reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(unsigned RegNo) const {
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reg_bundle_nodbg_iterator reg_bundle_nodbg_begin(Register RegNo) const {
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return reg_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static reg_bundle_nodbg_iterator reg_bundle_nodbg_end() {
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@ -368,7 +368,7 @@ public:
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}
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inline iterator_range<reg_bundle_nodbg_iterator>
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reg_nodbg_bundles(unsigned Reg) const {
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reg_nodbg_bundles(Register Reg) const {
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return make_range(reg_bundle_nodbg_begin(Reg), reg_bundle_nodbg_end());
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}
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@ -381,12 +381,12 @@ public:
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/// def_iterator/def_begin/def_end - Walk all defs of the specified register.
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using def_iterator =
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defusechain_iterator<false, true, false, true, false, false>;
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def_iterator def_begin(unsigned RegNo) const {
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def_iterator def_begin(Register RegNo) const {
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return def_iterator(getRegUseDefListHead(RegNo));
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}
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static def_iterator def_end() { return def_iterator(nullptr); }
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inline iterator_range<def_iterator> def_operands(unsigned Reg) const {
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inline iterator_range<def_iterator> def_operands(Register Reg) const {
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return make_range(def_begin(Reg), def_end());
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}
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@ -394,7 +394,7 @@ public:
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/// specified register, stepping by MachineInst.
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using def_instr_iterator =
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defusechain_instr_iterator<false, true, false, false, true, false>;
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def_instr_iterator def_instr_begin(unsigned RegNo) const {
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def_instr_iterator def_instr_begin(Register RegNo) const {
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return def_instr_iterator(getRegUseDefListHead(RegNo));
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}
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static def_instr_iterator def_instr_end() {
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@ -402,7 +402,7 @@ public:
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}
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inline iterator_range<def_instr_iterator>
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def_instructions(unsigned Reg) const {
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def_instructions(Register Reg) const {
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return make_range(def_instr_begin(Reg), def_instr_end());
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}
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@ -410,26 +410,26 @@ public:
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/// specified register, stepping by bundle.
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using def_bundle_iterator =
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defusechain_instr_iterator<false, true, false, false, false, true>;
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def_bundle_iterator def_bundle_begin(unsigned RegNo) const {
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def_bundle_iterator def_bundle_begin(Register RegNo) const {
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return def_bundle_iterator(getRegUseDefListHead(RegNo));
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}
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static def_bundle_iterator def_bundle_end() {
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return def_bundle_iterator(nullptr);
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}
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inline iterator_range<def_bundle_iterator> def_bundles(unsigned Reg) const {
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inline iterator_range<def_bundle_iterator> def_bundles(Register Reg) const {
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return make_range(def_bundle_begin(Reg), def_bundle_end());
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}
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/// def_empty - Return true if there are no instructions defining the
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/// specified register (it may be live-in).
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bool def_empty(unsigned RegNo) const { return def_begin(RegNo) == def_end(); }
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bool def_empty(Register RegNo) const { return def_begin(RegNo) == def_end(); }
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StringRef getVRegName(unsigned Reg) const {
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StringRef getVRegName(Register Reg) const {
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return VReg2Name.inBounds(Reg) ? StringRef(VReg2Name[Reg]) : "";
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}
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void insertVRegByName(StringRef Name, unsigned Reg) {
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void insertVRegByName(StringRef Name, Register Reg) {
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assert((Name.empty() || VRegNames.find(Name) == VRegNames.end()) &&
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"Named VRegs Must be Unique.");
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if (!Name.empty()) {
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@ -441,7 +441,7 @@ public:
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/// Return true if there is exactly one operand defining the specified
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/// register.
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bool hasOneDef(unsigned RegNo) const {
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bool hasOneDef(Register RegNo) const {
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def_iterator DI = def_begin(RegNo);
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if (DI == def_end())
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return false;
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@ -451,12 +451,12 @@ public:
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/// use_iterator/use_begin/use_end - Walk all uses of the specified register.
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using use_iterator =
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defusechain_iterator<true, false, false, true, false, false>;
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use_iterator use_begin(unsigned RegNo) const {
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use_iterator use_begin(Register RegNo) const {
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return use_iterator(getRegUseDefListHead(RegNo));
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}
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static use_iterator use_end() { return use_iterator(nullptr); }
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inline iterator_range<use_iterator> use_operands(unsigned Reg) const {
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inline iterator_range<use_iterator> use_operands(Register Reg) const {
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return make_range(use_begin(Reg), use_end());
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}
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@ -464,7 +464,7 @@ public:
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/// specified register, stepping by MachineInstr.
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using use_instr_iterator =
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defusechain_instr_iterator<true, false, false, false, true, false>;
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use_instr_iterator use_instr_begin(unsigned RegNo) const {
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use_instr_iterator use_instr_begin(Register RegNo) const {
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return use_instr_iterator(getRegUseDefListHead(RegNo));
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}
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static use_instr_iterator use_instr_end() {
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@ -472,7 +472,7 @@ public:
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}
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inline iterator_range<use_instr_iterator>
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use_instructions(unsigned Reg) const {
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use_instructions(Register Reg) const {
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return make_range(use_instr_begin(Reg), use_instr_end());
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}
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@ -480,24 +480,24 @@ public:
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/// specified register, stepping by bundle.
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using use_bundle_iterator =
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defusechain_instr_iterator<true, false, false, false, false, true>;
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use_bundle_iterator use_bundle_begin(unsigned RegNo) const {
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use_bundle_iterator use_bundle_begin(Register RegNo) const {
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return use_bundle_iterator(getRegUseDefListHead(RegNo));
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}
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static use_bundle_iterator use_bundle_end() {
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return use_bundle_iterator(nullptr);
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}
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inline iterator_range<use_bundle_iterator> use_bundles(unsigned Reg) const {
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inline iterator_range<use_bundle_iterator> use_bundles(Register Reg) const {
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return make_range(use_bundle_begin(Reg), use_bundle_end());
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}
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/// use_empty - Return true if there are no instructions using the specified
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/// register.
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bool use_empty(unsigned RegNo) const { return use_begin(RegNo) == use_end(); }
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bool use_empty(Register RegNo) const { return use_begin(RegNo) == use_end(); }
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/// hasOneUse - Return true if there is exactly one instruction using the
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/// specified register.
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bool hasOneUse(unsigned RegNo) const {
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bool hasOneUse(Register RegNo) const {
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use_iterator UI = use_begin(RegNo);
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if (UI == use_end())
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return false;
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@ -508,7 +508,7 @@ public:
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/// specified register, skipping those marked as Debug.
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using use_nodbg_iterator =
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defusechain_iterator<true, false, true, true, false, false>;
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use_nodbg_iterator use_nodbg_begin(unsigned RegNo) const {
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use_nodbg_iterator use_nodbg_begin(Register RegNo) const {
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return use_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static use_nodbg_iterator use_nodbg_end() {
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@ -516,7 +516,7 @@ public:
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}
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inline iterator_range<use_nodbg_iterator>
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use_nodbg_operands(unsigned Reg) const {
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use_nodbg_operands(Register Reg) const {
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return make_range(use_nodbg_begin(Reg), use_nodbg_end());
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}
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@ -525,7 +525,7 @@ public:
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/// those marked as Debug.
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using use_instr_nodbg_iterator =
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defusechain_instr_iterator<true, false, true, false, true, false>;
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use_instr_nodbg_iterator use_instr_nodbg_begin(unsigned RegNo) const {
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use_instr_nodbg_iterator use_instr_nodbg_begin(Register RegNo) const {
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return use_instr_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static use_instr_nodbg_iterator use_instr_nodbg_end() {
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@ -533,7 +533,7 @@ public:
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}
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inline iterator_range<use_instr_nodbg_iterator>
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use_nodbg_instructions(unsigned Reg) const {
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use_nodbg_instructions(Register Reg) const {
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return make_range(use_instr_nodbg_begin(Reg), use_instr_nodbg_end());
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}
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@ -542,7 +542,7 @@ public:
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/// those marked as Debug.
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using use_bundle_nodbg_iterator =
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defusechain_instr_iterator<true, false, true, false, false, true>;
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use_bundle_nodbg_iterator use_bundle_nodbg_begin(unsigned RegNo) const {
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use_bundle_nodbg_iterator use_bundle_nodbg_begin(Register RegNo) const {
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return use_bundle_nodbg_iterator(getRegUseDefListHead(RegNo));
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}
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static use_bundle_nodbg_iterator use_bundle_nodbg_end() {
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@ -550,25 +550,25 @@ public:
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}
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inline iterator_range<use_bundle_nodbg_iterator>
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use_nodbg_bundles(unsigned Reg) const {
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use_nodbg_bundles(Register Reg) const {
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return make_range(use_bundle_nodbg_begin(Reg), use_bundle_nodbg_end());
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}
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/// use_nodbg_empty - Return true if there are no non-Debug instructions
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/// using the specified register.
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bool use_nodbg_empty(unsigned RegNo) const {
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bool use_nodbg_empty(Register RegNo) const {
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return use_nodbg_begin(RegNo) == use_nodbg_end();
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}
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/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
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/// use of the specified register.
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bool hasOneNonDBGUse(unsigned RegNo) const;
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bool hasOneNonDBGUse(Register RegNo) const;
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/// hasOneNonDBGUse - Return true if there is exactly one non-Debug
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/// instruction using the specified register. Said instruction may have
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/// multiple uses.
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bool hasOneNonDBGUser(unsigned RegNo) const;
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bool hasOneNonDBGUser(Register RegNo) const;
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|
||||
/// replaceRegWith - Replace all instances of FromReg with ToReg in the
|
||||
/// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
|
||||
/// except that it also changes any definitions of the register as well.
|
||||
|
|
@ -588,33 +588,33 @@ public:
|
|||
/// Note that if ToReg is a physical register the function will replace and
|
||||
/// apply sub registers to ToReg in order to obtain a final/proper physical
|
||||
/// register.
|
||||
void replaceRegWith(unsigned FromReg, unsigned ToReg);
|
||||
void replaceRegWith(Register FromReg, Register ToReg);
|
||||
|
||||
/// getVRegDef - Return the machine instr that defines the specified virtual
|
||||
/// register or null if none is found. This assumes that the code is in SSA
|
||||
/// form, so there should only be one definition.
|
||||
MachineInstr *getVRegDef(unsigned Reg) const;
|
||||
MachineInstr *getVRegDef(Register Reg) const;
|
||||
|
||||
/// getUniqueVRegDef - Return the unique machine instr that defines the
|
||||
/// specified virtual register or null if none is found. If there are
|
||||
/// multiple definitions or no definition, return null.
|
||||
MachineInstr *getUniqueVRegDef(unsigned Reg) const;
|
||||
MachineInstr *getUniqueVRegDef(Register Reg) const;
|
||||
|
||||
/// clearKillFlags - Iterate over all the uses of the given register and
|
||||
/// clear the kill flag from the MachineOperand. This function is used by
|
||||
/// optimization passes which extend register lifetimes and need only
|
||||
/// preserve conservative kill flag information.
|
||||
void clearKillFlags(unsigned Reg) const;
|
||||
void clearKillFlags(Register Reg) const;
|
||||
|
||||
void dumpUses(unsigned RegNo) const;
|
||||
void dumpUses(Register RegNo) const;
|
||||
|
||||
/// Returns true if PhysReg is unallocatable and constant throughout the
|
||||
/// function. Writing to a constant register has no effect.
|
||||
bool isConstantPhysReg(unsigned PhysReg) const;
|
||||
bool isConstantPhysReg(MCRegister PhysReg) const;
|
||||
|
||||
/// Returns true if either isConstantPhysReg or TRI->isCallerPreservedPhysReg
|
||||
/// returns true. This is a utility member function.
|
||||
bool isCallerPreservedOrConstPhysReg(unsigned PhysReg) const;
|
||||
bool isCallerPreservedOrConstPhysReg(MCRegister PhysReg) const;
|
||||
|
||||
/// Get an iterator over the pressure sets affected by the given physical or
|
||||
/// virtual register. If RegUnit is physical, it must be a register unit (from
|
||||
|
|
@ -645,7 +645,7 @@ public:
|
|||
/// None of this condition is possible without GlobalISel for now.
|
||||
/// In other words, if GlobalISel is not used or if the query happens after
|
||||
/// the select pass, using getRegClass is safe.
|
||||
const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
|
||||
const TargetRegisterClass *getRegClassOrNull(Register Reg) const {
|
||||
const RegClassOrRegBank &Val = VRegInfo[Reg].first;
|
||||
return Val.dyn_cast<const TargetRegisterClass *>();
|
||||
}
|
||||
|
|
@ -654,7 +654,7 @@ public:
|
|||
/// a register bank or has been assigned a register class.
|
||||
/// \note It is possible to get the register bank from the register class via
|
||||
/// RegisterBankInfo::getRegBankFromRegClass.
|
||||
const RegisterBank *getRegBankOrNull(unsigned Reg) const {
|
||||
const RegisterBank *getRegBankOrNull(Register Reg) const {
|
||||
const RegClassOrRegBank &Val = VRegInfo[Reg].first;
|
||||
return Val.dyn_cast<const RegisterBank *>();
|
||||
}
|
||||
|
|
@ -662,17 +662,17 @@ public:
|
|||
/// Return the register bank or register class of \p Reg.
|
||||
/// \note Before the register bank gets assigned (i.e., before the
|
||||
/// RegBankSelect pass) \p Reg may not have either.
|
||||
const RegClassOrRegBank &getRegClassOrRegBank(unsigned Reg) const {
|
||||
const RegClassOrRegBank &getRegClassOrRegBank(Register Reg) const {
|
||||
return VRegInfo[Reg].first;
|
||||
}
|
||||
|
||||
/// setRegClass - Set the register class of the specified virtual register.
|
||||
void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
|
||||
void setRegClass(Register Reg, const TargetRegisterClass *RC);
|
||||
|
||||
/// Set the register bank to \p RegBank for \p Reg.
|
||||
void setRegBank(unsigned Reg, const RegisterBank &RegBank);
|
||||
void setRegBank(Register Reg, const RegisterBank &RegBank);
|
||||
|
||||
void setRegClassOrRegBank(unsigned Reg,
|
||||
void setRegClassOrRegBank(Register Reg,
|
||||
const RegClassOrRegBank &RCOrRB){
|
||||
VRegInfo[Reg].first = RCOrRB;
|
||||
}
|
||||
|
|
@ -688,7 +688,7 @@ public:
|
|||
/// Use RegisterBankInfo::constrainGenericRegister in GlobalISel's
|
||||
/// InstructionSelect pass and constrainRegAttrs in every other pass,
|
||||
/// including non-select passes of GlobalISel, instead.
|
||||
const TargetRegisterClass *constrainRegClass(unsigned Reg,
|
||||
const TargetRegisterClass *constrainRegClass(Register Reg,
|
||||
const TargetRegisterClass *RC,
|
||||
unsigned MinNumRegs = 0);
|
||||
|
||||
|
|
@ -703,7 +703,7 @@ public:
|
|||
/// \note Use this method instead of constrainRegClass and
|
||||
/// RegisterBankInfo::constrainGenericRegister everywhere but SelectionDAG
|
||||
/// ISel / FastISel and GlobalISel's InstructionSelect pass respectively.
|
||||
bool constrainRegAttrs(unsigned Reg, unsigned ConstrainingReg,
|
||||
bool constrainRegAttrs(Register Reg, Register ConstrainingReg,
|
||||
unsigned MinNumRegs = 0);
|
||||
|
||||
/// recomputeRegClass - Try to find a legal super-class of Reg's register
|
||||
|
|
@ -713,7 +713,7 @@ public:
|
|||
/// This method can be used after constraints have been removed from a
|
||||
/// virtual register, for example after removing instructions or splitting
|
||||
/// the live range.
|
||||
bool recomputeRegClass(unsigned Reg);
|
||||
bool recomputeRegClass(Register Reg);
|
||||
|
||||
/// createVirtualRegister - Create and return a new virtual register in the
|
||||
/// function with the specified register class.
|
||||
|
|
@ -726,14 +726,14 @@ public:
|
|||
|
||||
/// Get the low-level type of \p Reg or LLT{} if Reg is not a generic
|
||||
/// (target independent) virtual register.
|
||||
LLT getType(unsigned Reg) const {
|
||||
LLT getType(Register Reg) const {
|
||||
if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
|
||||
return VRegToType[Reg];
|
||||
return LLT{};
|
||||
}
|
||||
|
||||
/// Set the low-level type of \p VReg to \p Ty.
|
||||
void setType(unsigned VReg, LLT Ty);
|
||||
void setType(Register VReg, LLT Ty);
|
||||
|
||||
/// Create and return a new generic virtual register with low-level
|
||||
/// type \p Ty.
|
||||
|
|
@ -759,7 +759,7 @@ public:
|
|||
/// setRegAllocationHint - Specify a register allocation hint for the
|
||||
/// specified virtual register. This is typically used by target, and in case
|
||||
/// of an earlier hint it will be overwritten.
|
||||
void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) {
|
||||
void setRegAllocationHint(Register VReg, unsigned Type, Register PrefReg) {
|
||||
assert(Register::isVirtualRegister(VReg));
|
||||
RegAllocHints[VReg].first = Type;
|
||||
RegAllocHints[VReg].second.clear();
|
||||
|
|
@ -768,14 +768,14 @@ public:
|
|||
|
||||
/// addRegAllocationHint - Add a register allocation hint to the hints
|
||||
/// vector for VReg.
|
||||
void addRegAllocationHint(unsigned VReg, unsigned PrefReg) {
|
||||
void addRegAllocationHint(Register VReg, Register PrefReg) {
|
||||
assert(Register::isVirtualRegister(VReg));
|
||||
RegAllocHints[VReg].second.push_back(PrefReg);
|
||||
}
|
||||
|
||||
/// Specify the preferred (target independent) register allocation hint for
|
||||
/// the specified virtual register.
|
||||
void setSimpleHint(unsigned VReg, unsigned PrefReg) {
|
||||
void setSimpleHint(Register VReg, Register PrefReg) {
|
||||
setRegAllocationHint(VReg, /*Type=*/0, PrefReg);
|
||||
}
|
||||
|
||||
|
|
@ -816,11 +816,11 @@ public:
|
|||
/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
|
||||
/// specified register as undefined which causes the DBG_VALUE to be
|
||||
/// deleted during LiveDebugVariables analysis.
|
||||
void markUsesInDebugValueAsUndef(unsigned Reg) const;
|
||||
void markUsesInDebugValueAsUndef(Register Reg) const;
|
||||
|
||||
/// updateDbgUsersToReg - Update a collection of DBG_VALUE instructions
|
||||
/// to refer to the designated register.
|
||||
void updateDbgUsersToReg(unsigned Reg,
|
||||
void updateDbgUsersToReg(Register Reg,
|
||||
ArrayRef<MachineInstr*> Users) const {
|
||||
for (MachineInstr *MI : Users) {
|
||||
assert(MI->isDebugInstr());
|
||||
|
|
@ -835,13 +835,13 @@ public:
|
|||
/// ignored, to consider them pass 'true' for optional parameter
|
||||
/// SkipNoReturnDef. The register is also considered modified when it is set
|
||||
/// in the UsedPhysRegMask.
|
||||
bool isPhysRegModified(unsigned PhysReg, bool SkipNoReturnDef = false) const;
|
||||
bool isPhysRegModified(MCRegister PhysReg, bool SkipNoReturnDef = false) const;
|
||||
|
||||
/// Return true if the specified register is modified or read in this
|
||||
/// function. This checks that no machine operands exist for the register or
|
||||
/// any of its aliases. The register is also considered used when it is set
|
||||
/// in the UsedPhysRegMask.
|
||||
bool isPhysRegUsed(unsigned PhysReg) const;
|
||||
bool isPhysRegUsed(MCRegister PhysReg) const;
|
||||
|
||||
/// addPhysRegsUsedFromRegMask - Mark any registers not in RegMask as used.
|
||||
/// This corresponds to the bit mask attached to register mask operands.
|
||||
|
|
@ -923,31 +923,31 @@ public:
|
|||
|
||||
/// addLiveIn - Add the specified register as a live-in. Note that it
|
||||
/// is an error to add the same register to the same set more than once.
|
||||
void addLiveIn(unsigned Reg, unsigned vreg = 0) {
|
||||
void addLiveIn(MCRegister Reg, Register vreg = Register()) {
|
||||
LiveIns.push_back(std::make_pair(Reg, vreg));
|
||||
}
|
||||
|
||||
// Iteration support for the live-ins set. It's kept in sorted order
|
||||
// by register number.
|
||||
using livein_iterator =
|
||||
std::vector<std::pair<unsigned,unsigned>>::const_iterator;
|
||||
std::vector<std::pair<MCRegister,Register>>::const_iterator;
|
||||
livein_iterator livein_begin() const { return LiveIns.begin(); }
|
||||
livein_iterator livein_end() const { return LiveIns.end(); }
|
||||
bool livein_empty() const { return LiveIns.empty(); }
|
||||
|
||||
ArrayRef<std::pair<unsigned, unsigned>> liveins() const {
|
||||
ArrayRef<std::pair<MCRegister, Register>> liveins() const {
|
||||
return LiveIns;
|
||||
}
|
||||
|
||||
bool isLiveIn(unsigned Reg) const;
|
||||
bool isLiveIn(Register Reg) const;
|
||||
|
||||
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
|
||||
/// corresponding live-in physical register.
|
||||
unsigned getLiveInPhysReg(unsigned VReg) const;
|
||||
unsigned getLiveInPhysReg(Register VReg) const;
|
||||
|
||||
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
|
||||
/// corresponding live-in physical register.
|
||||
unsigned getLiveInVirtReg(unsigned PReg) const;
|
||||
unsigned getLiveInVirtReg(MCRegister PReg) const;
|
||||
|
||||
/// EmitLiveInCopies - Emit copies to initialize livein virtual registers
|
||||
/// into the given entry block.
|
||||
|
|
@ -957,7 +957,7 @@ public:
|
|||
|
||||
/// Returns a mask covering all bits that can appear in lane masks of
|
||||
/// subregisters of the virtual register @p Reg.
|
||||
LaneBitmask getMaxLaneMaskForVReg(unsigned Reg) const;
|
||||
LaneBitmask getMaxLaneMaskForVReg(Register Reg) const;
|
||||
|
||||
/// defusechain_iterator - This class provides iterator support for machine
|
||||
/// operands in the function that use or define a specific register. If
|
||||
|
|
|
|||
|
|
@ -27,9 +27,9 @@
|
|||
|
||||
using namespace llvm;
|
||||
|
||||
unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
|
||||
Register llvm::constrainRegToClass(MachineRegisterInfo &MRI,
|
||||
const TargetInstrInfo &TII,
|
||||
const RegisterBankInfo &RBI, unsigned Reg,
|
||||
const RegisterBankInfo &RBI, Register Reg,
|
||||
const TargetRegisterClass &RegClass) {
|
||||
if (!RBI.constrainGenericRegister(Reg, RegClass, MRI))
|
||||
return MRI.createVirtualRegister(&RegClass);
|
||||
|
|
@ -37,7 +37,7 @@ unsigned llvm::constrainRegToClass(MachineRegisterInfo &MRI,
|
|||
return Reg;
|
||||
}
|
||||
|
||||
unsigned llvm::constrainOperandRegClass(
|
||||
Register llvm::constrainOperandRegClass(
|
||||
const MachineFunction &MF, const TargetRegisterInfo &TRI,
|
||||
MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
|
||||
const RegisterBankInfo &RBI, MachineInstr &InsertPt,
|
||||
|
|
@ -47,7 +47,7 @@ unsigned llvm::constrainOperandRegClass(
|
|||
// Assume physical registers are properly constrained.
|
||||
assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
|
||||
|
||||
unsigned ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
|
||||
Register ConstrainedReg = constrainRegToClass(MRI, TII, RBI, Reg, RegClass);
|
||||
// If we created a new virtual register because the class is not compatible
|
||||
// then create a copy between the new and the old register.
|
||||
if (ConstrainedReg != Reg) {
|
||||
|
|
@ -67,7 +67,7 @@ unsigned llvm::constrainOperandRegClass(
|
|||
return ConstrainedReg;
|
||||
}
|
||||
|
||||
unsigned llvm::constrainOperandRegClass(
|
||||
Register llvm::constrainOperandRegClass(
|
||||
const MachineFunction &MF, const TargetRegisterInfo &TRI,
|
||||
MachineRegisterInfo &MRI, const TargetInstrInfo &TII,
|
||||
const RegisterBankInfo &RBI, MachineInstr &InsertPt, const MCInstrDesc &II,
|
||||
|
|
@ -204,7 +204,7 @@ void llvm::reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
|
|||
reportGISelFailure(MF, TPC, MORE, R);
|
||||
}
|
||||
|
||||
Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
|
||||
Optional<int64_t> llvm::getConstantVRegVal(Register VReg,
|
||||
const MachineRegisterInfo &MRI) {
|
||||
Optional<ValueAndVReg> ValAndVReg =
|
||||
getConstantVRegValWithLookThrough(VReg, MRI, /*LookThroughInstrs*/ false);
|
||||
|
|
@ -216,7 +216,7 @@ Optional<int64_t> llvm::getConstantVRegVal(unsigned VReg,
|
|||
}
|
||||
|
||||
Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(
|
||||
unsigned VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
|
||||
Register VReg, const MachineRegisterInfo &MRI, bool LookThroughInstrs,
|
||||
bool HandleFConstant) {
|
||||
SmallVector<std::pair<unsigned, unsigned>, 4> SeenOpcodes;
|
||||
MachineInstr *MI;
|
||||
|
|
@ -292,7 +292,7 @@ Optional<ValueAndVReg> llvm::getConstantVRegValWithLookThrough(
|
|||
return ValueAndVReg{Val.getSExtValue(), VReg};
|
||||
}
|
||||
|
||||
const llvm::ConstantFP* llvm::getConstantFPVRegVal(unsigned VReg,
|
||||
const llvm::ConstantFP* llvm::getConstantFPVRegVal(Register VReg,
|
||||
const MachineRegisterInfo &MRI) {
|
||||
MachineInstr *MI = MRI.getVRegDef(VReg);
|
||||
if (TargetOpcode::G_FCONSTANT != MI->getOpcode())
|
||||
|
|
|
|||
|
|
@ -450,8 +450,7 @@ void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr *> &Dead,
|
|||
// Keep track of new virtual registers created via
|
||||
// MachineRegisterInfo::createVirtualRegister.
|
||||
void
|
||||
LiveRangeEdit::MRI_NoteNewVirtualRegister(unsigned VReg)
|
||||
{
|
||||
LiveRangeEdit::MRI_NoteNewVirtualRegister(Register VReg) {
|
||||
if (VRM)
|
||||
VRM->grow();
|
||||
|
||||
|
|
|
|||
|
|
@ -55,18 +55,18 @@ MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
|
|||
/// setRegClass - Set the register class of the specified virtual register.
|
||||
///
|
||||
void
|
||||
MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
|
||||
MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) {
|
||||
assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
|
||||
VRegInfo[Reg].first = RC;
|
||||
}
|
||||
|
||||
void MachineRegisterInfo::setRegBank(unsigned Reg,
|
||||
void MachineRegisterInfo::setRegBank(Register Reg,
|
||||
const RegisterBank &RegBank) {
|
||||
VRegInfo[Reg].first = &RegBank;
|
||||
}
|
||||
|
||||
static const TargetRegisterClass *
|
||||
constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg,
|
||||
constrainRegClass(MachineRegisterInfo &MRI, Register Reg,
|
||||
const TargetRegisterClass *OldRC,
|
||||
const TargetRegisterClass *RC, unsigned MinNumRegs) {
|
||||
if (OldRC == RC)
|
||||
|
|
@ -82,15 +82,15 @@ constrainRegClass(MachineRegisterInfo &MRI, unsigned Reg,
|
|||
}
|
||||
|
||||
const TargetRegisterClass *
|
||||
MachineRegisterInfo::constrainRegClass(unsigned Reg,
|
||||
MachineRegisterInfo::constrainRegClass(Register Reg,
|
||||
const TargetRegisterClass *RC,
|
||||
unsigned MinNumRegs) {
|
||||
return ::constrainRegClass(*this, Reg, getRegClass(Reg), RC, MinNumRegs);
|
||||
}
|
||||
|
||||
bool
|
||||
MachineRegisterInfo::constrainRegAttrs(unsigned Reg,
|
||||
unsigned ConstrainingReg,
|
||||
MachineRegisterInfo::constrainRegAttrs(Register Reg,
|
||||
Register ConstrainingReg,
|
||||
unsigned MinNumRegs) {
|
||||
const LLT RegTy = getType(Reg);
|
||||
const LLT ConstrainingRegTy = getType(ConstrainingReg);
|
||||
|
|
@ -119,7 +119,7 @@ MachineRegisterInfo::constrainRegAttrs(unsigned Reg,
|
|||
}
|
||||
|
||||
bool
|
||||
MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
|
||||
MachineRegisterInfo::recomputeRegClass(Register Reg) {
|
||||
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
|
||||
const TargetRegisterClass *OldRC = getRegClass(Reg);
|
||||
const TargetRegisterClass *NewRC =
|
||||
|
|
@ -144,7 +144,7 @@ MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
|
|||
}
|
||||
|
||||
unsigned MachineRegisterInfo::createIncompleteVirtualRegister(StringRef Name) {
|
||||
unsigned Reg = Register::index2VirtReg(getNumVirtRegs());
|
||||
Register Reg = Register::index2VirtReg(getNumVirtRegs());
|
||||
VRegInfo.grow(Reg);
|
||||
RegAllocHints.grow(Reg);
|
||||
insertVRegByName(Name, Reg);
|
||||
|
|
@ -162,7 +162,7 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
|
|||
"Virtual register RegClass must be allocatable.");
|
||||
|
||||
// New virtual register number.
|
||||
unsigned Reg = createIncompleteVirtualRegister(Name);
|
||||
Register Reg = createIncompleteVirtualRegister(Name);
|
||||
VRegInfo[Reg].first = RegClass;
|
||||
if (TheDelegate)
|
||||
TheDelegate->MRI_NoteNewVirtualRegister(Reg);
|
||||
|
|
@ -171,7 +171,7 @@ MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
|
|||
|
||||
Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
|
||||
StringRef Name) {
|
||||
unsigned Reg = createIncompleteVirtualRegister(Name);
|
||||
Register Reg = createIncompleteVirtualRegister(Name);
|
||||
VRegInfo[Reg].first = VRegInfo[VReg].first;
|
||||
setType(Reg, getType(VReg));
|
||||
if (TheDelegate)
|
||||
|
|
@ -179,7 +179,7 @@ Register MachineRegisterInfo::cloneVirtualRegister(Register VReg,
|
|||
return Reg;
|
||||
}
|
||||
|
||||
void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
|
||||
void MachineRegisterInfo::setType(Register VReg, LLT Ty) {
|
||||
VRegToType.grow(VReg);
|
||||
VRegToType[VReg] = Ty;
|
||||
}
|
||||
|
|
@ -187,7 +187,7 @@ void MachineRegisterInfo::setType(unsigned VReg, LLT Ty) {
|
|||
Register
|
||||
MachineRegisterInfo::createGenericVirtualRegister(LLT Ty, StringRef Name) {
|
||||
// New virtual register number.
|
||||
unsigned Reg = createIncompleteVirtualRegister(Name);
|
||||
Register Reg = createIncompleteVirtualRegister(Name);
|
||||
// FIXME: Should we use a dummy register class?
|
||||
VRegInfo[Reg].first = static_cast<RegisterBank *>(nullptr);
|
||||
setType(Reg, Ty);
|
||||
|
|
@ -202,7 +202,7 @@ void MachineRegisterInfo::clearVirtRegTypes() { VRegToType.clear(); }
|
|||
void MachineRegisterInfo::clearVirtRegs() {
|
||||
#ifndef NDEBUG
|
||||
for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
|
||||
unsigned Reg = Register::index2VirtReg(i);
|
||||
Register Reg = Register::index2VirtReg(i);
|
||||
if (!VRegInfo[Reg].second)
|
||||
continue;
|
||||
verifyUseList(Reg);
|
||||
|
|
@ -214,7 +214,7 @@ void MachineRegisterInfo::clearVirtRegs() {
|
|||
I.second = 0;
|
||||
}
|
||||
|
||||
void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
|
||||
void MachineRegisterInfo::verifyUseList(Register Reg) const {
|
||||
#ifndef NDEBUG
|
||||
bool Valid = true;
|
||||
for (MachineOperand &M : reg_operands(Reg)) {
|
||||
|
|
@ -377,7 +377,7 @@ void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
|
|||
/// except that it also changes any definitions of the register as well.
|
||||
/// If ToReg is a physical register we apply the sub register to obtain the
|
||||
/// final/proper physical register.
|
||||
void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
|
||||
void MachineRegisterInfo::replaceRegWith(Register FromReg, Register ToReg) {
|
||||
assert(FromReg != ToReg && "Cannot replace a reg with itself");
|
||||
|
||||
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
|
||||
|
|
@ -397,7 +397,7 @@ void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
|
|||
/// getVRegDef - Return the machine instr that defines the specified virtual
|
||||
/// register or null if none is found. This assumes that the code is in SSA
|
||||
/// form, so there should only be one definition.
|
||||
MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
|
||||
MachineInstr *MachineRegisterInfo::getVRegDef(Register Reg) const {
|
||||
// Since we are in SSA form, we can use the first definition.
|
||||
def_instr_iterator I = def_instr_begin(Reg);
|
||||
assert((I.atEnd() || std::next(I) == def_instr_end()) &&
|
||||
|
|
@ -408,7 +408,7 @@ MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
|
|||
/// getUniqueVRegDef - Return the unique machine instr that defines the
|
||||
/// specified virtual register or null if none is found. If there are
|
||||
/// multiple definitions or no definition, return null.
|
||||
MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
|
||||
MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const {
|
||||
if (def_empty(Reg)) return nullptr;
|
||||
def_instr_iterator I = def_instr_begin(Reg);
|
||||
if (std::next(I) != def_instr_end())
|
||||
|
|
@ -416,14 +416,14 @@ MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
|
|||
return &*I;
|
||||
}
|
||||
|
||||
bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
|
||||
bool MachineRegisterInfo::hasOneNonDBGUse(Register RegNo) const {
|
||||
use_nodbg_iterator UI = use_nodbg_begin(RegNo);
|
||||
if (UI == use_nodbg_end())
|
||||
return false;
|
||||
return ++UI == use_nodbg_end();
|
||||
}
|
||||
|
||||
bool MachineRegisterInfo::hasOneNonDBGUser(unsigned RegNo) const {
|
||||
bool MachineRegisterInfo::hasOneNonDBGUser(Register RegNo) const {
|
||||
use_instr_nodbg_iterator UI = use_instr_nodbg_begin(RegNo);
|
||||
if (UI == use_instr_nodbg_end())
|
||||
return false;
|
||||
|
|
@ -434,21 +434,21 @@ bool MachineRegisterInfo::hasOneNonDBGUser(unsigned RegNo) const {
|
|||
/// clear the kill flag from the MachineOperand. This function is used by
|
||||
/// optimization passes which extend register lifetimes and need only
|
||||
/// preserve conservative kill flag information.
|
||||
void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
|
||||
void MachineRegisterInfo::clearKillFlags(Register Reg) const {
|
||||
for (MachineOperand &MO : use_operands(Reg))
|
||||
MO.setIsKill(false);
|
||||
}
|
||||
|
||||
bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
|
||||
bool MachineRegisterInfo::isLiveIn(Register Reg) const {
|
||||
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
|
||||
if (I->first == Reg || I->second == Reg)
|
||||
if ((Register)I->first == Reg || I->second == Reg)
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
|
||||
/// getLiveInPhysReg - If VReg is a live-in virtual register, return the
|
||||
/// corresponding live-in physical register.
|
||||
unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
|
||||
unsigned MachineRegisterInfo::getLiveInPhysReg(Register VReg) const {
|
||||
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
|
||||
if (I->second == VReg)
|
||||
return I->first;
|
||||
|
|
@ -457,7 +457,7 @@ unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
|
|||
|
||||
/// getLiveInVirtReg - If PReg is a live-in physical register, return the
|
||||
/// corresponding live-in physical register.
|
||||
unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
|
||||
unsigned MachineRegisterInfo::getLiveInVirtReg(MCRegister PReg) const {
|
||||
for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
|
||||
if (I->first == PReg)
|
||||
return I->second;
|
||||
|
|
@ -496,7 +496,7 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
|
|||
}
|
||||
}
|
||||
|
||||
LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const {
|
||||
LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(Register Reg) const {
|
||||
// Lane masks are only defined for vregs.
|
||||
assert(Register::isVirtualRegister(Reg));
|
||||
const TargetRegisterClass &TRC = *getRegClass(Reg);
|
||||
|
|
@ -504,7 +504,7 @@ LaneBitmask MachineRegisterInfo::getMaxLaneMaskForVReg(unsigned Reg) const {
|
|||
}
|
||||
|
||||
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
|
||||
LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(unsigned Reg) const {
|
||||
LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const {
|
||||
for (MachineInstr &I : use_instructions(Reg))
|
||||
I.dump();
|
||||
}
|
||||
|
|
@ -516,7 +516,7 @@ void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
|
|||
"Invalid ReservedRegs vector from target");
|
||||
}
|
||||
|
||||
bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
|
||||
bool MachineRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
|
||||
assert(Register::isPhysicalRegister(PhysReg));
|
||||
|
||||
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
|
||||
|
|
@ -533,7 +533,7 @@ bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg) const {
|
|||
}
|
||||
|
||||
bool
|
||||
MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const {
|
||||
MachineRegisterInfo::isCallerPreservedOrConstPhysReg(MCRegister PhysReg) const {
|
||||
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
|
||||
return isConstantPhysReg(PhysReg) ||
|
||||
TRI->isCallerPreservedPhysReg(PhysReg, *MF);
|
||||
|
|
@ -542,7 +542,7 @@ MachineRegisterInfo::isCallerPreservedOrConstPhysReg(unsigned PhysReg) const {
|
|||
/// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
|
||||
/// specified register as undefined which causes the DBG_VALUE to be
|
||||
/// deleted during LiveDebugVariables analysis.
|
||||
void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
|
||||
void MachineRegisterInfo::markUsesInDebugValueAsUndef(Register Reg) const {
|
||||
// Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
|
||||
MachineRegisterInfo::use_instr_iterator nextI;
|
||||
for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
|
||||
|
|
@ -583,7 +583,7 @@ static bool isNoReturnDef(const MachineOperand &MO) {
|
|||
!Called->hasFnAttribute(Attribute::NoUnwind));
|
||||
}
|
||||
|
||||
bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg,
|
||||
bool MachineRegisterInfo::isPhysRegModified(MCRegister PhysReg,
|
||||
bool SkipNoReturnDef) const {
|
||||
if (UsedPhysRegMask.test(PhysReg))
|
||||
return true;
|
||||
|
|
@ -598,7 +598,7 @@ bool MachineRegisterInfo::isPhysRegModified(unsigned PhysReg,
|
|||
return false;
|
||||
}
|
||||
|
||||
bool MachineRegisterInfo::isPhysRegUsed(unsigned PhysReg) const {
|
||||
bool MachineRegisterInfo::isPhysRegUsed(MCRegister PhysReg) const {
|
||||
if (UsedPhysRegMask.test(PhysReg))
|
||||
return true;
|
||||
const TargetRegisterInfo *TRI = getTargetRegisterInfo();
|
||||
|
|
|
|||
Loading…
Reference in New Issue