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Add a check in the ARM disassembler for NEON instructions that would 

reference registers past the end of the NEON register file, and report them
as invalid instead of asserting when trying to print them.  PR7746.

llvm-svn: 109933
This commit is contained in:
Bob Wilson 2010-07-30 23:27:59 +00:00
parent 719ed7d058
commit eb7b21f3eb
1 changed files with 9 additions and 5 deletions
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14
llvm/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -2248,9 +2248,10 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
// We have homogeneous NEON registers for Load/Store.
unsigned RegClass = 0;
bool DRegPair = UseDRegPair(Opcode);
// Double-spaced registers have increments of 2.
unsigned Inc = DblSpaced ? 2 : 1;
unsigned Inc = (DblSpaced || DRegPair) ? 2 : 1;
unsigned Rn = decodeRn(insn);
unsigned Rm = decodeRm(insn);
@ -2296,8 +2297,7 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
RegClass = OpInfo[OpIdx].RegClass;
while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
MI.addOperand(MCOperand::CreateReg(
getRegisterEnum(B, RegClass, Rd,
UseDRegPair(Opcode))));
getRegisterEnum(B, RegClass, Rd, DRegPair)));
Rd += Inc;
++OpIdx;
}
@ -2316,8 +2316,7 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
MI.addOperand(MCOperand::CreateReg(
getRegisterEnum(B, RegClass, Rd,
UseDRegPair(Opcode))));
getRegisterEnum(B, RegClass, Rd, DRegPair)));
Rd += Inc;
++OpIdx;
}
@ -2355,6 +2354,11 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
}
}
// Accessing registers past the end of the NEON register file is not
// defined.
if (Rd > 32)
return false;
return true;
}