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AMDGPU/GlobalISel: Allow selection of scalar min/max 

I believe all of the uniform/divergent pattern predicates are
redundant and can be removed. The uniformity bit already influences
the register class, and nothhing has broken when I've removed this and
others.

llvm-svn: 372450
This commit is contained in:
Matt Arsenault 2019-09-21 02:37:33 +00:00
parent bd7f2354cc
commit eb6eb694e4
5 changed files with 24 additions and 44 deletions
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8
llvm/lib/Target/AMDGPU/SOPInstructions.td
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@ -419,16 +419,16 @@ def S_SUBB_U32 : SOP2_32 <"s_subb_u32",
let isCommutable = 1 in { let isCommutable = 1 in {
def S_MIN_I32 : SOP2_32 <"s_min_i32", def S_MIN_I32 : SOP2_32 <"s_min_i32",
[(set i32:$sdst, (UniformBinFrag<smin> i32:$src0, i32:$src1))] [(set i32:$sdst, (smin i32:$src0, i32:$src1))]
>; >;
def S_MIN_U32 : SOP2_32 <"s_min_u32", def S_MIN_U32 : SOP2_32 <"s_min_u32",
[(set i32:$sdst, (UniformBinFrag<umin> i32:$src0, i32:$src1))] [(set i32:$sdst, (umin i32:$src0, i32:$src1))]
>; >;
def S_MAX_I32 : SOP2_32 <"s_max_i32", def S_MAX_I32 : SOP2_32 <"s_max_i32",
[(set i32:$sdst, (UniformBinFrag<smax> i32:$src0, i32:$src1))] [(set i32:$sdst, (smax i32:$src0, i32:$src1))]
>; >;
def S_MAX_U32 : SOP2_32 <"s_max_u32", def S_MAX_U32 : SOP2_32 <"s_max_u32",
[(set i32:$sdst, (UniformBinFrag<umax> i32:$src0, i32:$src1))] [(set i32:$sdst, (umax i32:$src0, i32:$src1))]
>; >;
} // End isCommutable = 1 } // End isCommutable = 1
} // End Defs = [SCC] } // End Defs = [SCC]

15
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
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@ -1,10 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: FileCheck -check-prefix=ERR %s < %t
# ERR-NOT: remark:
# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_SMAX %0:sgpr, %1:sgpr (in function: smax_s32_ss)
# ERR-NOT: remark:
--- ---
name: smax_s32_ss name: smax_s32_ss
@ -15,10 +10,10 @@ body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GCN-LABEL: name: smax_s32_ss ; GCN-LABEL: name: smax_s32_ss
; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[COPY1]] ; GCN: [[S_MAX_I32_:%[0-9]+]]:sreg_32 = S_MAX_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: S_ENDPGM 0, implicit [[SMAX]](s32) ; GCN: S_ENDPGM 0, implicit [[S_MAX_I32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_SMAX %0, %1 %2:sgpr(s32) = G_SMAX %0, %1

15
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
View File

@ -1,10 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: FileCheck -check-prefix=ERR %s < %t
# ERR-NOT: remark:
# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_SMIN %0:sgpr, %1:sgpr (in function: smin_s32_ss)
# ERR-NOT: remark:
--- ---
name: smin_s32_ss name: smin_s32_ss
@ -15,10 +10,10 @@ body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GCN-LABEL: name: smin_s32_ss ; GCN-LABEL: name: smin_s32_ss
; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[COPY]], [[COPY1]] ; GCN: [[S_MIN_I32_:%[0-9]+]]:sreg_32 = S_MIN_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: S_ENDPGM 0, implicit [[SMIN]](s32) ; GCN: S_ENDPGM 0, implicit [[S_MIN_I32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_SMIN %0, %1 %2:sgpr(s32) = G_SMIN %0, %1

15
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
View File

@ -1,10 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: FileCheck -check-prefix=ERR %s < %t
# ERR-NOT: remark:
# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_UMAX %0:sgpr, %1:sgpr (in function: umax_s32_ss)
# ERR-NOT: remark:
--- ---
name: umax_s32_ss name: umax_s32_ss
@ -15,10 +10,10 @@ body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GCN-LABEL: name: umax_s32_ss ; GCN-LABEL: name: umax_s32_ss
; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[COPY]], [[COPY1]] ; GCN: [[S_MAX_U32_:%[0-9]+]]:sreg_32 = S_MAX_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: S_ENDPGM 0, implicit [[UMAX]](s32) ; GCN: S_ENDPGM 0, implicit [[S_MAX_U32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_UMAX %0, %1 %2:sgpr(s32) = G_UMAX %0, %1

15
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
View File

@ -1,10 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
# RUN: FileCheck -check-prefix=ERR %s < %t
# ERR-NOT: remark:
# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_UMIN %0:sgpr, %1:sgpr (in function: umin_s32_ss)
# ERR-NOT: remark:
--- ---
name: umin_s32_ss name: umin_s32_ss
@ -15,10 +10,10 @@ body: |
bb.0: bb.0:
liveins: $sgpr0, $sgpr1 liveins: $sgpr0, $sgpr1
; GCN-LABEL: name: umin_s32_ss ; GCN-LABEL: name: umin_s32_ss
; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1 ; GCN: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GCN: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[COPY]], [[COPY1]] ; GCN: [[S_MIN_U32_:%[0-9]+]]:sreg_32 = S_MIN_U32 [[COPY]], [[COPY1]], implicit-def $scc
; GCN: S_ENDPGM 0, implicit [[UMIN]](s32) ; GCN: S_ENDPGM 0, implicit [[S_MIN_U32_]]
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1 %1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_UMIN %0, %1 %2:sgpr(s32) = G_UMIN %0, %1