forked from OSchip/llvm-project
ARM: remove now unneeded custom Asm converters
After Ulrich's r180677 (thanks!) TableGen is intelligent enough to handle tied constraints involving complex operands properly, so virtually all of the ARM custom converters are now unnecessary. llvm-svn: 186810
This commit is contained in:
Tim Northover
parent
d0ed3a417e
commit
eb5e4d532c
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@ -2293,7 +2293,6 @@ multiclass AI2_ldridx<bit isByte, string opc,
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let Inst{19-16} = addr{16-13};
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let Inst{11-0} = addr{11-0};
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let DecoderMethod = "DecodeLDRPreImm";
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let AsmMatchConverter = "cvtLdWriteBackRegAddrModeImm12";
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}
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def _PRE_REG : AI2ldstidx<1, isByte, 1, (outs GPR:$Rt, GPR:$Rn_wb),
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@ -2306,7 +2305,6 @@ multiclass AI2_ldridx<bit isByte, string opc,
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let Inst{11-0} = addr{11-0};
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let Inst{4} = 0;
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let DecoderMethod = "DecodeLDRPreReg";
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode2";
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}
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def _POST_REG : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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@ -2364,7 +2362,6 @@ multiclass AI3_ldridx<bits<4> op, string opc, InstrItinClass itin> {
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let AsmMatchConverter = "cvtLdWriteBackRegAddrMode3";
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let DecoderMethod = "DecodeAddrMode3Instruction";
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}
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def _POST : AI3ldstidx<op, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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@ -2400,7 +2397,6 @@ def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let DecoderMethod = "DecodeAddrMode3Instruction";
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let AsmMatchConverter = "cvtLdrdPre";
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}
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def LDRD_POST: AI3ldstidx<0b1101, 0, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
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(ins addr_offset_none:$addr, am3offset:$offset),
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@ -2503,7 +2499,6 @@ multiclass AI3ldrT<bits<4> op, string opc> {
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let Inst{22} = 1;
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let Inst{11-8} = offset{7-4};
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let Inst{3-0} = offset{3-0};
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let AsmMatchConverter = "cvtLdExtTWriteBackImm";
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}
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def r : AI3ldstidxT<op, 1, (outs GPRnopc:$Rt, GPRnopc:$base_wb),
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(ins addr_offset_none:$addr, postidx_reg:$Rm),
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@ -2515,7 +2510,6 @@ multiclass AI3ldrT<bits<4> op, string opc> {
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let Inst{11-8} = 0;
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let Unpredictable{11-8} = 0b1111;
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let Inst{3-0} = Rm{3-0};
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let AsmMatchConverter = "cvtLdExtTWriteBackReg";
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let DecoderMethod = "DecodeLDR";
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}
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}
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@ -2553,7 +2547,6 @@ multiclass AI2_stridx<bit isByte, string opc,
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let Inst{23} = addr{12}; // U (add = ('U' == 1))
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{11-0} = addr{11-0}; // imm12
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let AsmMatchConverter = "cvtStWriteBackRegAddrModeImm12";
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let DecoderMethod = "DecodeSTRPreImm";
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}
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@ -2567,7 +2560,6 @@ multiclass AI2_stridx<bit isByte, string opc,
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let Inst{19-16} = addr{16-13}; // Rn
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let Inst{11-0} = addr{11-0};
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let Inst{4} = 0; // Inst{4} = 0
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let AsmMatchConverter = "cvtStWriteBackRegAddrMode2";
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let DecoderMethod = "DecodeSTRPreReg";
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}
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def _POST_REG : AI2ldstidx<0, isByte, 0, (outs GPR:$Rn_wb),
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@ -2676,7 +2668,6 @@ def STRH_PRE : AI3ldstidx<0b1011, 0, 1, (outs GPR:$Rn_wb),
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let Inst{19-16} = addr{12-9}; // Rn
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let AsmMatchConverter = "cvtStWriteBackRegAddrMode3";
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let DecoderMethod = "DecodeAddrMode3Instruction";
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}
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@ -2710,7 +2701,6 @@ def STRD_PRE : AI3ldstidx<0b1111, 0, 1, (outs GPR:$Rn_wb),
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let Inst{11-8} = addr{7-4}; // imm7_4/zero
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let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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let DecoderMethod = "DecodeAddrMode3Instruction";
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let AsmMatchConverter = "cvtStrdPre";
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}
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def STRD_POST: AI3ldstidx<0b1111, 0, 0, (outs GPR:$Rn_wb),
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@ -2817,7 +2807,6 @@ multiclass AI3strT<bits<4> op, string opc> {
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let Inst{22} = 1;
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let Inst{11-8} = offset{7-4};
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let Inst{3-0} = offset{3-0};
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let AsmMatchConverter = "cvtStExtTWriteBackImm";
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}
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def r : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
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(ins GPR:$Rt, addr_offset_none:$addr, postidx_reg:$Rm),
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@ -2828,7 +2817,6 @@ multiclass AI3strT<bits<4> op, string opc> {
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let Inst{22} = 0;
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let Inst{11-8} = 0;
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let Inst{3-0} = Rm{3-0};
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let AsmMatchConverter = "cvtStExtTWriteBackReg";
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}
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}
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@ -656,7 +656,6 @@ multiclass VLD1DWB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
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@ -664,7 +663,6 @@ multiclass VLD1DWB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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multiclass VLD1QWB<bits<4> op7_4, string Dt> {
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@ -675,7 +673,6 @@ multiclass VLD1QWB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
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@ -683,7 +680,6 @@ multiclass VLD1QWB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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@ -713,7 +709,6 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
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@ -721,7 +716,6 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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@ -754,7 +748,6 @@ multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
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@ -762,7 +755,6 @@ multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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@ -811,7 +803,6 @@ multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST2Instruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm), itin,
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@ -819,7 +810,6 @@ multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST2Instruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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@ -1348,7 +1338,6 @@ multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLD1DupInstruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<1, 0b10, 0b1100, op7_4,
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(outs VecListOneDAllLanes:$Vd, GPR:$wb),
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@ -1357,7 +1346,6 @@ multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLD1DupInstruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
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@ -1369,7 +1357,6 @@ multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLD1DupInstruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<1, 0b10, 0b1100, op7_4,
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(outs VecListDPairAllLanes:$Vd, GPR:$wb),
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@ -1378,7 +1365,6 @@ multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLD1DupInstruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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@ -1419,7 +1405,6 @@ multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLD2DupInstruction";
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let AsmMatchConverter = "cvtVLDwbFixed";
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}
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def _register : NLdSt<1, 0b10, 0b1101, op7_4,
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(outs VdTy:$Vd, GPR:$wb),
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@ -1428,7 +1413,6 @@ multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> {
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLD2DupInstruction";
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let AsmMatchConverter = "cvtVLDwbRegister";
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}
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}
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@ -1609,7 +1593,6 @@ multiclass VST1DWB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
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@ -1618,7 +1601,6 @@ multiclass VST1DWB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{4} = Rn{4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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multiclass VST1QWB<bits<4> op7_4, string Dt> {
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@ -1629,7 +1611,6 @@ multiclass VST1QWB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListDPair:$Vd),
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@ -1638,7 +1619,6 @@ multiclass VST1QWB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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@ -1669,7 +1649,6 @@ multiclass VST1D3WB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
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@ -1678,7 +1657,6 @@ multiclass VST1D3WB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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@ -1714,7 +1692,6 @@ multiclass VST1D4WB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
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@ -1723,7 +1700,6 @@ multiclass VST1D4WB<bits<4> op7_4, string Dt> {
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST1Instruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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@ -1773,7 +1749,6 @@ multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST2Instruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
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@ -1781,7 +1756,6 @@ multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
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"$Rn.addr = $wb", []> {
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST2Instruction";
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let AsmMatchConverter = "cvtVSTwbRegister";
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}
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}
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multiclass VST2QWB<bits<4> op7_4, string Dt> {
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@ -1792,7 +1766,6 @@ multiclass VST2QWB<bits<4> op7_4, string Dt> {
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let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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let Inst{5-4} = Rn{5-4};
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let DecoderMethod = "DecodeVLDST2Instruction";
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let AsmMatchConverter = "cvtVSTwbFixed";
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}
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def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
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(ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
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@ -1801,7 +1774,6 @@ multiclass VST2QWB<bits<4> op7_4, string Dt> {
|
|||
"$Rn.addr = $wb", []> {
|
||||
let Inst{5-4} = Rn{5-4};
|
||||
let DecoderMethod = "DecodeVLDST2Instruction";
|
||||
let AsmMatchConverter = "cvtVSTwbRegister";
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1318,10 +1318,7 @@ let mayLoad = 1, neverHasSideEffects = 1 in {
|
|||
def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_iu,
|
||||
"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
|
||||
[]> {
|
||||
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
"ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
|
||||
|
||||
def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
|
||||
|
|
@ -1331,10 +1328,8 @@ def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
|
|||
def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
|
||||
[]> {
|
||||
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
"ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
|
||||
|
||||
def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
|
|
@ -1343,10 +1338,8 @@ def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
|
|||
def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
|
||||
[]> {
|
||||
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
"ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", []>;
|
||||
|
||||
def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
|
|
@ -1356,9 +1349,8 @@ def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
|
|||
(ins t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
|
||||
[]> {
|
||||
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
[]>;
|
||||
|
||||
def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
|
|
@ -1368,9 +1360,8 @@ def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
|
|||
(ins t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
|
||||
"ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb",
|
||||
[]> {
|
||||
let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
[]>;
|
||||
|
||||
def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
|
||||
(ins addr_offset_none:$Rn, t2am_imm8_offset:$offset),
|
||||
AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu,
|
||||
|
|
@ -1426,24 +1417,19 @@ def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb),
|
|||
(ins GPRnopc:$Rt, t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
|
||||
"str", "\t$Rt, $addr!",
|
||||
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
|
||||
let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
|
||||
|
||||
def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
|
||||
(ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iStore_iu,
|
||||
"strh", "\t$Rt, $addr!",
|
||||
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
|
||||
let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
|
||||
|
||||
def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb),
|
||||
(ins rGPR:$Rt, t2addrmode_imm8_pre:$addr),
|
||||
AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu,
|
||||
"strb", "\t$Rt, $addr!",
|
||||
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> {
|
||||
let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8";
|
||||
}
|
||||
"$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []>;
|
||||
} // mayStore = 1, neverHasSideEffects = 1
|
||||
|
||||
def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb),
|
||||
|
|
@ -1532,7 +1518,6 @@ def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
|
|||
def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb),
|
||||
(ins t2addrmode_imm8s4_pre:$addr), IIC_iLoad_d_ru,
|
||||
"ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> {
|
||||
let AsmMatchConverter = "cvtT2LdrdPre";
|
||||
let DecoderMethod = "DecodeT2LDRDPreInstruction";
|
||||
}
|
||||
|
||||
|
|
@ -1545,7 +1530,6 @@ def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb),
|
|||
(ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4_pre:$addr),
|
||||
IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!",
|
||||
"$addr.base = $wb", []> {
|
||||
let AsmMatchConverter = "cvtT2StrdPre";
|
||||
let DecoderMethod = "DecodeT2STRDPreInstruction";
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -219,44 +219,8 @@ class ARMAsmParser : public MCTargetAsmParser {
|
|||
SMLoc &EndLoc);
|
||||
|
||||
// Asm Match Converter Methods
|
||||
void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtStWriteBackRegAddrMode2(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtStWriteBackRegAddrMode3(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtLdExtTWriteBackImm(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtLdExtTWriteBackReg(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtStExtTWriteBackImm(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtStExtTWriteBackReg(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtThumbMultiply(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtVLDwbFixed(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtVLDwbRegister(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtVSTwbFixed(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
void cvtVSTwbRegister(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &);
|
||||
bool validateInstruction(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
|
||||
bool processInstruction(MCInst &Inst,
|
||||
|
|
@ -4077,260 +4041,9 @@ parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
|||
return MatchOperand_Success;
|
||||
}
|
||||
|
||||
/// cvtT2LdrdPre - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtT2LdrdPre(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Rt, Rt2
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateReg(0));
|
||||
// addr
|
||||
((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtT2StrdPre - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtT2StrdPre(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateReg(0));
|
||||
// Rt, Rt2
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
|
||||
// addr
|
||||
((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
|
||||
((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtLdWriteBackRegAddrMode2(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
|
||||
((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
|
||||
((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
|
||||
/// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtStWriteBackRegAddrMode2(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtStWriteBackRegAddrMode3(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtLdExtTWriteBackImm(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Rt
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// addr
|
||||
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
|
||||
// offset
|
||||
((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtLdExtTWriteBackReg(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Rt
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// addr
|
||||
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
|
||||
// offset
|
||||
((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtStExtTWriteBackImm(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// Rt
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
// addr
|
||||
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
|
||||
// offset
|
||||
((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtStExtTWriteBackReg(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// Rt
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
// addr
|
||||
((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
|
||||
// offset
|
||||
((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtLdrdPre - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtLdrdPre(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Rt, Rt2
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// addr
|
||||
((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtStrdPre - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtStrdPre(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// Rt, Rt2
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
|
||||
// addr
|
||||
((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
void ARMAsmParser::
|
||||
cvtLdWriteBackRegAddrMode3(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// cvtThumbMultiply - Convert parsed operands to MCInst.
|
||||
/// Needed here because the Asm Gen Matcher can't handle properly tied operands
|
||||
/// when they refer multiple MIOperands inside a single one.
|
||||
/// Convert parsed operands to MCInst. Needed here because this instruction
|
||||
/// only has two register operands, but multiplication is commutative so
|
||||
/// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
|
||||
void ARMAsmParser::
|
||||
cvtThumbMultiply(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
|
|
@ -4348,62 +4061,6 @@ cvtThumbMultiply(MCInst &Inst,
|
|||
((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
void ARMAsmParser::
|
||||
cvtVLDwbFixed(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Vd
|
||||
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// Vn
|
||||
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
void ARMAsmParser::
|
||||
cvtVLDwbRegister(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Vd
|
||||
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// Vn
|
||||
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
|
||||
// Vm
|
||||
((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
void ARMAsmParser::
|
||||
cvtVSTwbFixed(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// Vn
|
||||
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
|
||||
// Vt
|
||||
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
void ARMAsmParser::
|
||||
cvtVSTwbRegister(MCInst &Inst,
|
||||
const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
|
||||
// Create a writeback register dummy placeholder.
|
||||
Inst.addOperand(MCOperand::CreateImm(0));
|
||||
// Vn
|
||||
((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
|
||||
// Vm
|
||||
((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
|
||||
// Vt
|
||||
((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
|
||||
// pred
|
||||
((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
|
||||
}
|
||||
|
||||
/// Parse an ARM memory expression, return false if successful else return true
|
||||
/// or an error. The first token must be a '[' when called.
|
||||
bool ARMAsmParser::
|
||||
|
|
|
|||
Loading…
Reference in New Issue