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[Hexagon] Handle HVX/FP {masked,wide} loads/stores 

Co-authored-by: Rahul Utkoor <quic_rutkoor@quicinc.com>
Co-authored-by: Anirudh Sundar Subramaniam <quic_sanirudh@quicinc.com>
This commit is contained in:
Krzysztof Parzyszek 2021-12-30 09:03:31 -08:00
parent 8792cd75d0
commit eb574259b6
2 changed files with 27 additions and 0 deletions
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10
llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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@ -119,6 +119,16 @@ HexagonTargetLowering::initializeHVXLowering() {
// Make concat-vectors custom to handle concats of more than 2 vectors.
setOperationAction(ISD::CONCAT_VECTORS, MVT::v128f16, Custom);
setOperationAction(ISD::CONCAT_VECTORS, MVT::v64f32, Custom);
setOperationAction(ISD::LOAD, MVT::v64f32, Custom);
setOperationAction(ISD::STORE, MVT::v64f32, Custom);
setOperationAction(ISD::MLOAD, MVT::v32f32, Custom);
setOperationAction(ISD::MSTORE, MVT::v32f32, Custom);
setOperationAction(ISD::MLOAD, MVT::v64f16, Custom);
setOperationAction(ISD::MSTORE, MVT::v64f16, Custom);
setOperationAction(ISD::MLOAD, MVT::v64f32, Custom);
setOperationAction(ISD::MSTORE, MVT::v64f32, Custom);
}
for (MVT T : LegalV) {

17
llvm/test/CodeGen/Hexagon/autohvx/isel-mstore-fp16.ll Normal file
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@ -0,0 +1,17 @@
; RUN: llc -march=hexagon < %s | FileCheck %s
; Check for a non-crashing output.
; CHECK: vmem
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"
define dllexport void @fred() #0 {
tail call void @llvm.masked.store.v64f16.p0v64f16(<64 x half> <half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef, half 0xHFBFF, half undef>, <64 x half>* undef, i32 64, <64 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>)
ret void
}
; Function Attrs: argmemonly nounwind willreturn writeonly
declare void @llvm.masked.store.v64f16.p0v64f16(<64 x half>, <64 x half>*, i32 immarg, <64 x i1>) #0
attributes #0 = { argmemonly nounwind willreturn writeonly "target-cpu"="hexagonv69" "target-features"="+hvxv69,+hvx-length128b,+hvx-qfloat" }