forked from OSchip/llvm-project
do some serious surgery on CellSPU to get it back into a world
where it uses types consistently. llvm-svn: 98532
This commit is contained in:
Chris Lattner
parent
26e6273772
commit
eb319f36b9
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@ -205,10 +205,9 @@ def CellSDKnand:
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// Shift/rotate intrinsics:
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//===----------------------------------------------------------------------===//
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/* FIXME: These have (currently unenforced) type conflicts. */
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def CellSDKshli:
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Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val),
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(SHLIv4i32 VECREG:$rA, uimm7:$val)>;
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(SHLIv4i32 VECREG:$rA, (TO_IMM32 imm:$val))>;
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def CellSDKshlqbi:
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Pat<(int_spu_si_shlqbi VECREG:$rA, R32C:$rB),
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@ -216,7 +215,7 @@ def CellSDKshlqbi:
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def CellSDKshlqii:
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Pat<(int_spu_si_shlqbii VECREG:$rA, uimm7:$val),
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(SHLQBIIv16i8 VECREG:$rA, uimm7:$val)>;
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(SHLQBIIv16i8 VECREG:$rA, (TO_IMM32 imm:$val))>;
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def CellSDKshlqby:
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Pat<(int_spu_si_shlqby VECREG:$rA, R32C:$rB),
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@ -224,7 +223,8 @@ def CellSDKshlqby:
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def CellSDKshlqbyi:
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Pat<(int_spu_si_shlqbyi VECREG:$rA, uimm7:$val),
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(SHLQBYIv16i8 VECREG:$rA, uimm7:$val)>;
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(SHLQBYIv16i8 VECREG:$rA, (TO_IMM32 imm:$val))>;
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//===----------------------------------------------------------------------===//
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// Branch/compare intrinsics:
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@ -155,8 +155,9 @@ multiclass CompareLogicalGreaterEqual64 {
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defm I64LGE: CompareLogicalGreaterEqual64;
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def : Pat<(setuge R64C:$rA, R64C:$rB), I64LGEr64.Fragment>;
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def : Pat<(setuge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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I64LGEv2i64.Fragment>;
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def : Pat<(v2i64 (setuge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB))),
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I64LGEv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setult, I64LGEr64>;
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@ -233,8 +234,8 @@ multiclass CompareGreaterEqual64 {
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defm I64GE: CompareGreaterEqual64;
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def : Pat<(setge R64C:$rA, R64C:$rB), I64GEr64.Fragment>;
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def : Pat<(setge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB)),
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I64GEv2i64.Fragment>;
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def : Pat<(v2i64 (setge (v2i64 VECREG:$rA), (v2i64 VECREG:$rB))),
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I64GEv2i64.Fragment>;
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// i64 setult:
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def : I64SETCCNegCond<setlt, I64GEr64>;
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@ -2179,10 +2179,10 @@ multiclass ShiftLeftHalfwordImm
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defm SHLHI : ShiftLeftHalfwordImm;
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def : Pat<(SPUvec_shl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
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(SHLHIv8i16 VECREG:$rA, uimm7:$val)>;
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(SHLHIv8i16 VECREG:$rA, (TO_IMM16 uimm7:$val))>;
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def : Pat<(shl R16C:$rA, (i32 uimm7:$val)),
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(SHLHIr16 R16C:$rA, uimm7:$val)>;
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(SHLHIr16 R16C:$rA, (TO_IMM16 uimm7:$val))>;
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//===----------------------------------------------------------------------===//
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@ -2410,8 +2410,8 @@ multiclass RotateLeftHalfwordImm
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defm ROTHI: RotateLeftHalfwordImm;
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def : Pat<(SPUvec_rotl VECREG:$rA, (i32 uimm7:$val)),
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(ROTHIv8i16 VECREG:$rA, imm:$val)>;
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def : Pat<(SPUvec_rotl (v8i16 VECREG:$rA), (i32 uimm7:$val)),
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(ROTHIv8i16 VECREG:$rA, (TO_IMM16 imm:$val))>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// Rotate word:
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@ -2682,10 +2682,10 @@ def : Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i32 imm:$val)),
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(ROTHMIv8i16 VECREG:$rA, imm:$val)>;
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def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i16 imm:$val)),
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(ROTHMIv8i16 VECREG:$rA, imm:$val)>;
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(ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>;
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def: Pat<(SPUvec_srl (v8i16 VECREG:$rA), (i8 imm:$val)),
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(ROTHMIv8i16 VECREG:$rA, imm:$val)>;
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(ROTHMIv8i16 VECREG:$rA, (TO_IMM32 imm:$val))>;
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def ROTHMIr16:
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ROTHMIInst<(outs R16C:$rT), (ins R16C:$rA, rothNeg7imm:$val),
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@ -2695,10 +2695,10 @@ def: Pat<(srl R16C:$rA, (i32 uimm7:$val)),
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(ROTHMIr16 R16C:$rA, uimm7:$val)>;
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def: Pat<(srl R16C:$rA, (i16 uimm7:$val)),
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(ROTHMIr16 R16C:$rA, uimm7:$val)>;
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(ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
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def: Pat<(srl R16C:$rA, (i8 uimm7:$val)),
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(ROTHMIr16 R16C:$rA, uimm7:$val)>;
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(ROTHMIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
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// ROTM v4i32 form: See the ROTHM v8i16 comments.
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class ROTMInst<dag OOL, dag IOL, list<dag> pattern>:
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@ -2709,14 +2709,14 @@ def ROTMv4i32:
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ROTMInst<(outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
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[/* see patterns below - $rB must be negated */]>;
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def : Pat<(SPUvec_srl VECREG:$rA, R32C:$rB),
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R32C:$rB),
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(ROTMv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_srl VECREG:$rA, R16C:$rB),
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R16C:$rB),
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(ROTMv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 R16C:$rB), 0))>;
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def : Pat<(SPUvec_srl VECREG:$rA, R8C:$rB),
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), R8C:$rB),
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(ROTMv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
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@ -2742,11 +2742,11 @@ def ROTMIv4i32:
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[(set (v4i32 VECREG:$rT),
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(SPUvec_srl VECREG:$rA, (i32 uimm7:$val)))]>;
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def : Pat<(SPUvec_srl VECREG:$rA, (i16 uimm7:$val)),
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(ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i16 uimm7:$val)),
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(ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>;
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def : Pat<(SPUvec_srl VECREG:$rA, (i8 uimm7:$val)),
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(ROTMIv4i32 VECREG:$rA, uimm7:$val)>;
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def : Pat<(SPUvec_srl (v4i32 VECREG:$rA), (i8 uimm7:$val)),
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(ROTMIv4i32 VECREG:$rA, (TO_IMM32 uimm7:$val))>;
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// ROTMI r32 form: know how to complement the immediate value.
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def ROTMIr32:
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@ -2755,10 +2755,10 @@ def ROTMIr32:
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[(set R32C:$rT, (srl R32C:$rA, (i32 uimm7:$val)))]>;
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def : Pat<(srl R32C:$rA, (i16 imm:$val)),
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(ROTMIr32 R32C:$rA, uimm7:$val)>;
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(ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>;
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def : Pat<(srl R32C:$rA, (i8 imm:$val)),
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(ROTMIr32 R32C:$rA, uimm7:$val)>;
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(ROTMIr32 R32C:$rA, (TO_IMM32 uimm7:$val))>;
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//-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~
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// ROTQMBY: This is a vector form merely so that when used in an
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@ -2916,14 +2916,14 @@ def ROTMAHv8i16:
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"rotmah\t$rT, $rA, $rB", RotateShift,
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[/* see patterns below - $rB must be negated */]>;
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def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R32C:$rB),
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(ROTMAHv8i16 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R16C:$rB),
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(ROTMAHv8i16 VECREG:$rA,
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(SFIr32 (XSHWr16 R16C:$rB), 0))>;
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def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), R8C:$rB),
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(ROTMAHv8i16 VECREG:$rA,
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(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
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@ -2950,10 +2950,10 @@ def ROTMAHIv8i16:
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(SPUvec_sra (v8i16 VECREG:$rA), (i32 uimm7:$val)))]>;
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i16 uimm7:$val)),
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(ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
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(ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>;
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def : Pat<(SPUvec_sra (v8i16 VECREG:$rA), (i8 uimm7:$val)),
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(ROTMAHIv8i16 (v8i16 VECREG:$rA), (i32 uimm7:$val))>;
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(ROTMAHIv8i16 (v8i16 VECREG:$rA), (TO_IMM32 uimm7:$val))>;
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def ROTMAHIr16:
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RRForm<0b01111110000, (outs R16C:$rT), (ins R16C:$rA, rothNeg7imm_i16:$val),
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@ -2961,25 +2961,25 @@ def ROTMAHIr16:
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[(set R16C:$rT, (sra R16C:$rA, (i16 uimm7:$val)))]>;
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def : Pat<(sra R16C:$rA, (i32 imm:$val)),
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(ROTMAHIr16 R16C:$rA, uimm7:$val)>;
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(ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
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def : Pat<(sra R16C:$rA, (i8 imm:$val)),
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(ROTMAHIr16 R16C:$rA, uimm7:$val)>;
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(ROTMAHIr16 R16C:$rA, (TO_IMM32 uimm7:$val))>;
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def ROTMAv4i32:
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RRForm<0b01011010000, (outs VECREG:$rT), (ins VECREG:$rA, R32C:$rB),
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"rotma\t$rT, $rA, $rB", RotateShift,
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[/* see patterns below - $rB must be negated */]>;
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def : Pat<(SPUvec_sra VECREG:$rA, R32C:$rB),
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(ROTMAv4i32 (v4i32 VECREG:$rA), (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R32C:$rB),
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(ROTMAv4i32 VECREG:$rA, (SFIr32 R32C:$rB, 0))>;
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def : Pat<(SPUvec_sra VECREG:$rA, R16C:$rB),
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(ROTMAv4i32 (v4i32 VECREG:$rA),
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def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R16C:$rB),
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(ROTMAv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 R16C:$rB), 0))>;
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def : Pat<(SPUvec_sra VECREG:$rA, R8C:$rB),
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(ROTMAv4i32 (v4i32 VECREG:$rA),
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def : Pat<(SPUvec_sra (v4i32 VECREG:$rA), R8C:$rB),
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(ROTMAv4i32 VECREG:$rA,
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(SFIr32 (XSHWr16 (XSBHr8 R8C:$rB)), 0))>;
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def ROTMAr32:
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@ -9,6 +9,17 @@
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// Cell SPU Instruction Operands:
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//===----------------------------------------------------------------------===//
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// TO_IMM32 - Convert an i8/i16 to i32.
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def TO_IMM32 : SDNodeXForm<imm, [{
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return getI32Imm(N->getZExtValue());
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}]>;
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// TO_IMM16 - Convert an i8/i32 to i16.
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def TO_IMM16 : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i16);
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}]>;
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def LO16 : SDNodeXForm<imm, [{
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unsigned val = N->getZExtValue();
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// Transformation function: get the low 16 bits.
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