forked from OSchip/llvm-project
Use EmitCmp in SelectBranch. No functional change intended.
llvm-svn: 143076
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@ -1100,30 +1100,8 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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// If we can, avoid recomputing the compare - redoing it could lead to wonky
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// behavior.
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// TODO: Factor this out.
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if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
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MVT SourceVT;
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Type *Ty = CI->getOperand(0)->getType();
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if (CI->hasOneUse() && (CI->getParent() == I->getParent())
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&& isTypeLegal(Ty, SourceVT)) {
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bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
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if (isFloat && !Subtarget->hasVFP2())
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return false;
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unsigned CmpOpc;
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switch (SourceVT.SimpleTy) {
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default: return false;
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// TODO: Verify compares.
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case MVT::f32:
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CmpOpc = ARM::VCMPES;
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break;
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case MVT::f64:
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CmpOpc = ARM::VCMPED;
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break;
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case MVT::i32:
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CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
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break;
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}
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if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
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// Get the compare predicate.
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// Try to take advantage of fallthrough opportunities.
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@ -1138,19 +1116,14 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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// We may not handle every CC for now.
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if (ARMPred == ARMCC::AL) return false;
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unsigned Arg1 = getRegForValue(CI->getOperand(0));
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if (Arg1 == 0) return false;
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unsigned Arg2 = getRegForValue(CI->getOperand(1));
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if (Arg2 == 0) return false;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(CmpOpc))
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.addReg(Arg1).addReg(Arg2));
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// Emit the compare.
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Type *Ty = CI->getOperand(0)->getType();
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if (!ARMEmitCmp(Ty, CI->getOperand(0), CI->getOperand(1)))
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return false;
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// For floating point we need to move the result to a comparison register
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// that we can then use for branches.
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if (isFloat)
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if (Ty->isFloatTy() || Ty->isDoubleTy())
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::FMSTAT)));
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