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R600: Add pattern for SHA-256 Ma function 

This can be optimized using the BFI_INT instruction.

llvm-svn: 181033
This commit is contained in:
Tom Stellard 2013-05-03 17:21:20 +00:00
parent c2516c6e40
commit eac65dde30
4 changed files with 35 additions and 0 deletions
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8
llvm/lib/Target/R600/AMDGPUInstructions.td
View File

@ -276,6 +276,14 @@ multiclass BFIPatterns <Instruction BFI_INT> {
}
// SHA-256 Ma patterns
// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
(or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
(BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
>;
include "R600Instructions.td"
include "SIInstrInfo.td"

3
llvm/lib/Target/R600/R600Instructions.td
View File

@ -1669,6 +1669,9 @@ let hasSideEffects = 1 in {
def : Pat<(fp_to_uint f32:$src0), (FLT_TO_UINT_eg (TRUNC $src0))>;
// SHA-256 Patterns
def : SHA256MaPattern <BFI_INT_eg, XOR_INT>;
def EG_ExportSwz : ExportSwzInst {
let Word1{19-16} = 0; // BURST_COUNT
let Word1{20} = 1; // VALID_PIXEL_MODE

6
llvm/lib/Target/R600/SIInstructions.td
View File

@ -1592,4 +1592,10 @@ def : Pat<
(V_CMP_U_F32_e64 $src0, $src1)
>;
//============================================================================//
// Miscellaneous Optimization Patterns
//============================================================================//
def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>;
} // End isSI predicate

18
llvm/test/CodeGen/R600/bfi_int.ll
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@ -32,3 +32,21 @@ entry:
store i32 %2, i32 addrspace(1)* %out
ret void
}
; SHA-256 Ma function
; ((x & z) | (y & (x | z)))
; R600-CHECK: @bfi_sha256_ma
; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV.x}}, {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
; SI-CHECK: V_XOR_B32_e32 [[DST:VGPR[0-9]+]], {{VGPR[0-9]+, VGPR[0-9]+}}
; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{VGPR[0-9]+, VGPR[0-9]+}}
define void @bfi_sha256_ma(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
entry:
%0 = and i32 %x, %z
%1 = or i32 %x, %z
%2 = and i32 %y, %1
%3 = or i32 %0, %2
store i32 %3, i32 addrspace(1)* %out
ret void
}