maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[SelectionDAG] Correctly transform range metadata to AssertZExt 

We used the logBase2 of the high instead of the ceilLogBase2 resulting
in the wrong result for certain values.  For example, it resulted in an
i1 AssertZExt when the exclusive portion of the range was 3.

llvm-svn: 291196
This commit is contained in:
David Majnemer 2017-01-06 00:11:46 +00:00
parent 61f5473bad
commit eaba06cffa
2 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -7344,7 +7344,7 @@ SDValue SelectionDAGBuilder::lowerRangeToAssertZExt(SelectionDAG &DAG,
return Op;
Constant *Hi = cast<ConstantAsMetadata>(Range->getOperand(1))->getValue();
unsigned Bits = cast<ConstantInt>(Hi)->getValue().logBase2();
unsigned Bits = cast<ConstantInt>(Hi)->getValue().ceilLogBase2();
EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits);

18
llvm/test/CodeGen/NVPTX/tid-range.ll Normal file
View File

@ -0,0 +1,18 @@
; RUN: llc < %s -march=nvptx64 | FileCheck %s
declare i32 @get_register()
define i1 @test1() {
entry:
%call = call i32 @llvm.nvvm.read.ptx.sreg.tid.x(), !range !0
%cmp = icmp eq i32 %call, 1
ret i1 %cmp
}
; CHECK-LABEL: test1(
; CHECK: setp.eq.s32 %p1, %r1, 1;
; CHECK: selp.u32 %[[R:.+]], 1, 0, %p1;
; CHECK: st.param.b32 [func_retval0+0], %[[R]];
declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
!0 = !{ i32 0, i32 3 }