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[TargetLowering][RISCV] Don't transform (seteq/ne (sext_inreg X, VT), C1) -> (seteq/ne (zext_inreg X, VT), C1) if the sext_inreg is cheaper 

RISCV has to use 2 shifts for (i64 (zext_inreg X, i32)), but we
can use addiw rd, rs1, x0 for sext_inreg. We already understood this
when type legalizing i32 seteq/ne on rv64. But this transform in
SimplifySetCC would sometimes undo it.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D95289
This commit is contained in:
Craig Topper 2021-01-25 16:17:42 -08:00
parent f9b6fd269b
commit ea87cf2acd
4 changed files with 13 additions and 19 deletions
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4
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -3736,7 +3736,9 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
break; // todo, be more careful with signed comparisons
}
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
(Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
!isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(),
OpVT)) {
EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
EVT ExtDstTy = N0.getValueType();

7
llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
View File

@ -19,7 +19,7 @@ define double @func(double %d, i32 %n) nounwind {
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call func
; RV32IFD-NEXT: call func@plt
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld ft0, 16(sp)
@ -37,15 +37,14 @@ define double @func(double %d, i32 %n) nounwind {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: slli a2, a1, 32
; RV64IFD-NEXT: srli a2, a2, 32
; RV64IFD-NEXT: sext.w a2, a1
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func
; RV64IFD-NEXT: call func@plt
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fld ft1, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1

15
llvm/test/CodeGen/RISCV/setcc-logic.ll
View File

@ -18,8 +18,7 @@ define i1 @and_icmp_eq(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xor a1, a2, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%cmp1 = icmp eq i32 %a, %b
@ -42,8 +41,7 @@ define i1 @or_icmp_ne(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xor a1, a2, a3
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%cmp1 = icmp ne i32 %a, %b
@ -87,10 +85,8 @@ define i1 @and_icmps_const_1bit_diff(i32 %x) nounwind {
; RV64I-LABEL: and_icmps_const_1bit_diff:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, -44
; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: addi a1, a1, -17
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: andi a0, a0, -17
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ret
%a = icmp ne i32 %x, 44
@ -111,8 +107,7 @@ define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
;
; RV64I-LABEL: and_icmps_const_not1bit_diff:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a1, a0, -44
; RV64I-NEXT: snez a1, a1
; RV64I-NEXT: addi a0, a0, -92

6
llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
View File

@ -485,8 +485,7 @@ define i32 @sext_of_not_cmp_i32(i32 %x) {
;
; RV64I-LABEL: sext_of_not_cmp_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a0, a0, -7
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: neg a0, a0
@ -530,8 +529,7 @@ define i32 @dec_of_zexted_cmp_i32(i32 %x) {
;
; RV64I-LABEL: dec_of_zexted_cmp_i32:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: addi a0, a0, -7
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a0, a0, -1