forked from OSchip/llvm-project
[Test][AggressiveInstCombine] Add test for `udiv` and `urem`
Precommit test for D109515
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -aggressive-instcombine -S | FileCheck %s
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define i16 @udiv_one_arg(i8 %x) {
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; CHECK-LABEL: @udiv_one_arg(
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[ZEXT]], 42
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[DIV]] to i16
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; CHECK-NEXT: ret i16 [[TRUNC]]
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;
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%zext = zext i8 %x to i32
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%div = udiv i32 %zext, 42
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%trunc = trunc i32 %div to i16
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ret i16 %trunc
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}
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define i16 @udiv_two_args(i16 %x, i16 %y) {
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; CHECK-LABEL: @udiv_two_args(
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; CHECK-NEXT: [[ZEXTX:%.*]] = zext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[ZEXTY:%.*]] = zext i16 [[Y:%.*]] to i32
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; CHECK-NEXT: [[I0:%.*]] = udiv i32 [[ZEXTX]], [[ZEXTY]]
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; CHECK-NEXT: [[R:%.*]] = trunc i32 [[I0]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%zextx = zext i16 %x to i32
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%zexty = zext i16 %y to i32
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%i0 = udiv i32 %zextx, %zexty
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%r = trunc i32 %i0 to i16
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ret i16 %r
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}
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define i16 @udiv_big_const(i8 %x) {
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; CHECK-LABEL: @udiv_big_const(
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[ZEXT]], 70000
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[DIV]] to i16
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; CHECK-NEXT: ret i16 [[TRUNC]]
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;
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%zext = zext i8 %x to i32
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%div = udiv i32 %zext, 70000
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%trunc = trunc i32 %div to i16
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ret i16 %trunc
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}
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define <2 x i16> @udiv_vector(<2 x i8> %x) {
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; CHECK-LABEL: @udiv_vector(
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; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[S:%.*]] = udiv <2 x i32> [[Z]], <i32 4, i32 10>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T]]
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;
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%z = zext <2 x i8> %x to <2 x i32>
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%s = udiv <2 x i32> %z, <i32 4, i32 10>
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%t = trunc <2 x i32> %s to <2 x i16>
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ret <2 x i16> %t
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}
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define <2 x i8> @udiv_vector_need_new_vector_type(<2 x i8> %x) {
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; CHECK-LABEL: @udiv_vector_need_new_vector_type(
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; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[S:%.*]] = udiv <2 x i32> [[Z]], <i32 4, i32 500>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i8>
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; CHECK-NEXT: ret <2 x i8> [[T]]
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;
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%z = zext <2 x i8> %x to <2 x i32>
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%s = udiv <2 x i32> %z, <i32 4, i32 500>
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%t = trunc <2 x i32> %s to <2 x i8>
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ret <2 x i8> %t
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}
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define <2 x i16> @udiv_vector_big_const(<2 x i8> %x) {
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; CHECK-LABEL: @udiv_vector_big_const(
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; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[S:%.*]] = udiv <2 x i32> [[Z]], <i32 16, i32 70000>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T]]
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;
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%z = zext <2 x i8> %x to <2 x i32>
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%s = udiv <2 x i32> %z, <i32 16, i32 70000>
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%t = trunc <2 x i32> %s to <2 x i16>
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ret <2 x i16> %t
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}
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define i16 @udiv_exact(i16 %x, i16 %y) {
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; CHECK-LABEL: @udiv_exact(
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; CHECK-NEXT: [[ZEXTX:%.*]] = zext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[ZEXTY:%.*]] = zext i16 [[Y:%.*]] to i32
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; CHECK-NEXT: [[I0:%.*]] = udiv exact i32 [[ZEXTX]], [[ZEXTY]]
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; CHECK-NEXT: [[R:%.*]] = trunc i32 [[I0]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%zextx = zext i16 %x to i32
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%zexty = zext i16 %y to i32
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%i0 = udiv exact i32 %zextx, %zexty
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%r = trunc i32 %i0 to i16
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ret i16 %r
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}
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define i16 @urem_one_arg(i8 %x) {
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; CHECK-LABEL: @urem_one_arg(
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[DIV:%.*]] = urem i32 [[ZEXT]], 42
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[DIV]] to i16
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; CHECK-NEXT: ret i16 [[TRUNC]]
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;
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%zext = zext i8 %x to i32
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%div = urem i32 %zext, 42
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%trunc = trunc i32 %div to i16
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ret i16 %trunc
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}
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define i16 @urem_two_args(i16 %x, i16 %y) {
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; CHECK-LABEL: @urem_two_args(
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; CHECK-NEXT: [[ZEXTX:%.*]] = zext i16 [[X:%.*]] to i32
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; CHECK-NEXT: [[ZEXTY:%.*]] = zext i16 [[Y:%.*]] to i32
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; CHECK-NEXT: [[I0:%.*]] = urem i32 [[ZEXTX]], [[ZEXTY]]
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; CHECK-NEXT: [[R:%.*]] = trunc i32 [[I0]] to i16
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; CHECK-NEXT: ret i16 [[R]]
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;
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%zextx = zext i16 %x to i32
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%zexty = zext i16 %y to i32
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%i0 = urem i32 %zextx, %zexty
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%r = trunc i32 %i0 to i16
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ret i16 %r
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}
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define i16 @urem_big_const(i8 %x) {
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; CHECK-LABEL: @urem_big_const(
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; CHECK-NEXT: [[ZEXT:%.*]] = zext i8 [[X:%.*]] to i32
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; CHECK-NEXT: [[DIV:%.*]] = urem i32 [[ZEXT]], 70000
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; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[DIV]] to i16
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; CHECK-NEXT: ret i16 [[TRUNC]]
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;
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%zext = zext i8 %x to i32
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%div = urem i32 %zext, 70000
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%trunc = trunc i32 %div to i16
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ret i16 %trunc
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}
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define <2 x i16> @urem_vector(<2 x i8> %x) {
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; CHECK-LABEL: @urem_vector(
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; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[S:%.*]] = urem <2 x i32> [[Z]], <i32 4, i32 10>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T]]
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;
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%z = zext <2 x i8> %x to <2 x i32>
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%s = urem <2 x i32> %z, <i32 4, i32 10>
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%t = trunc <2 x i32> %s to <2 x i16>
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ret <2 x i16> %t
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}
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define <2 x i8> @urem_vector_need_new_vector_type(<2 x i8> %x) {
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; CHECK-LABEL: @urem_vector_need_new_vector_type(
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; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[S:%.*]] = urem <2 x i32> [[Z]], <i32 500, i32 10>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i8>
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; CHECK-NEXT: ret <2 x i8> [[T]]
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;
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%z = zext <2 x i8> %x to <2 x i32>
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%s = urem <2 x i32> %z, <i32 500, i32 10>
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%t = trunc <2 x i32> %s to <2 x i8>
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ret <2 x i8> %t
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}
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define <2 x i16> @urem_vector_big_const(<2 x i8> %x) {
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; CHECK-LABEL: @urem_vector_big_const(
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; CHECK-NEXT: [[Z:%.*]] = zext <2 x i8> [[X:%.*]] to <2 x i32>
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; CHECK-NEXT: [[S:%.*]] = urem <2 x i32> [[Z]], <i32 16, i32 70000>
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; CHECK-NEXT: [[T:%.*]] = trunc <2 x i32> [[S]] to <2 x i16>
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; CHECK-NEXT: ret <2 x i16> [[T]]
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;
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%z = zext <2 x i8> %x to <2 x i32>
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%s = urem <2 x i32> %z, <i32 16, i32 70000>
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%t = trunc <2 x i32> %s to <2 x i16>
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ret <2 x i16> %t
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}
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