From ea752cc50aae0a370deb1706463551d1ff8092a1 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sat, 17 Dec 2005 20:59:06 +0000 Subject: [PATCH] Add support for 64-bit arguments llvm-svn: 24792 --- llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp index a2eb9c7acb9d..a17637a46ab1 100644 --- a/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp +++ b/llvm/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp @@ -102,6 +102,18 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); } ArgValues.push_back(Arg); + break; + } + case MVT::i64: { + unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); + MF.addLiveIn(GPR[ArgNo++], VRegLo); + unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); + MF.addLiveIn(GPR[ArgNo++], VRegHi); + SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32); + SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32); + DAG.setRoot(ArgHi.getValue(1)); + ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi)); + break; } } }