forked from OSchip/llvm-project
[SelectionDAG] Use APInt::isNullValue/isOneValue. NFC
llvm-svn: 305605
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@ -2549,14 +2549,14 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
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!DAG.isConstantIntBuildVectorOrConstantInt(N1))
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return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
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// fold (mul x, 0) -> 0
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if (N1IsConst && ConstValue1 == 0)
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if (N1IsConst && ConstValue1.isNullValue())
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return N1;
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// We require a splat of the entire scalar bit width for non-contiguous
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// bit patterns.
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bool IsFullSplat =
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ConstValue1.getBitWidth() == VT.getScalarSizeInBits();
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// fold (mul x, 1) -> x
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if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
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if (N1IsConst && ConstValue1.isOneValue() && IsFullSplat)
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return N0;
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if (SDValue NewSel = foldBinOpIntoSelect(N))
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@ -919,7 +919,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
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// always convert this into a logical shr, even if the shift amount is
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// variable. The low bit of the shift cannot be an input sign bit unless
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// the shift amount is >= the size of the datatype, which is undefined.
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if (NewMask == 1)
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if (NewMask.isOneValue())
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return TLO.CombineTo(Op,
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TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
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Op.getOperand(0), Op.getOperand(1)));
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@ -1349,7 +1349,7 @@ bool TargetLowering::isConstTrueVal(const SDNode *N) const {
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case UndefinedBooleanContent:
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return CVal[0];
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case ZeroOrOneBooleanContent:
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return CVal == 1;
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return CVal.isOneValue();
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case ZeroOrNegativeOneBooleanContent:
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return CVal.isAllOnesValue();
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}
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@ -1506,7 +1506,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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// If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
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// equality comparison, then we're just comparing whether X itself is
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// zero.
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if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
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if (N0.getOpcode() == ISD::SRL && (C1.isNullValue() || C1.isOneValue()) &&
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N0.getOperand(0).getOpcode() == ISD::CTLZ &&
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N0.getOperand(1).getOpcode() == ISD::Constant) {
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const APInt &ShAmt
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