forked from OSchip/llvm-project
[Target] Introduce a generic opcode for bitwise OR: G_OR.
This G_OR is used in GlobalISel to represent bitwise OR. llvm-svn: 272160
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@ -12,6 +12,9 @@
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//
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//===----------------------------------------------------------------------===//
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//------------------------------------------------------------------------------
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// Binary ops.
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//------------------------------------------------------------------------------
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// Generic addition.
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def G_ADD : Instruction {
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let OutOperandList = (outs unknown:$dst);
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@ -21,6 +24,18 @@ def G_ADD : Instruction {
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let isCommutable = 1;
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}
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// Generic bitwise or.
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def G_OR : Instruction {
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let OutOperandList = (outs unknown:$dst);
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let InOperandList = (ins unknown:$src1, unknown:$src2);
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let AsmString = "";
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let hasSideEffects = 0;
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let isCommutable = 1;
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}
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//------------------------------------------------------------------------------
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// Branches.
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//------------------------------------------------------------------------------
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// Generic unconditional branch.
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def G_BR : Instruction {
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let OutOperandList = (outs);
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@ -150,8 +150,11 @@ HANDLE_TARGET_OPCODE(PATCHABLE_OP, 23)
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HANDLE_TARGET_OPCODE(G_ADD, 24)
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_START, G_ADD)
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/// Generic Bitwise-OR instruction.
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HANDLE_TARGET_OPCODE(G_OR, 25)
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/// Generic BRANCH instruction. This is an unconditional branch.
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HANDLE_TARGET_OPCODE(G_BR, 25)
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HANDLE_TARGET_OPCODE(G_BR, 26)
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// TODO: Add more generic opcodes as we move along.
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@ -36,8 +36,8 @@ def InstB : TestInstruction {
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// CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ...
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// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21
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// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18
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// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 27, 0, 0, 0, // Opcode: InstB, skip to: 18
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// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 26, 1, // Opcode: InstA
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// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 28, 0, 0, 0, // Opcode: InstB, skip to: 18
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// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 27, 1, // Opcode: InstA
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// CHECK-NEXT: /* 21 */ MCD::OPC_Fail,
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// CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
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@ -35,9 +35,9 @@ def InstB : TestInstruction {
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// CHECK-NEXT: /* 7 */ MCD::OPC_ExtractField, 5, 3, // Inst{7-5} ...
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// CHECK-NEXT: /* 10 */ MCD::OPC_FilterValue, 0, 22, 0, // Skip to: 36
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// CHECK-NEXT: /* 14 */ MCD::OPC_CheckField, 0, 2, 3, 5, 0, // Skip to: 25
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// CHECK-NEXT: /* 20 */ MCD::OPC_TryDecode, 27, 0, 0, 0, // Opcode: InstB, skip to: 25
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// CHECK-NEXT: /* 20 */ MCD::OPC_TryDecode, 28, 0, 0, 0, // Opcode: InstB, skip to: 25
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// CHECK-NEXT: /* 25 */ MCD::OPC_CheckField, 3, 2, 0, 5, 0, // Skip to: 36
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// CHECK-NEXT: /* 31 */ MCD::OPC_TryDecode, 26, 1, 0, 0, // Opcode: InstA, skip to: 36
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// CHECK-NEXT: /* 31 */ MCD::OPC_TryDecode, 27, 1, 0, 0, // Opcode: InstA, skip to: 36
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// CHECK-NEXT: /* 36 */ MCD::OPC_Fail,
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// CHECK: if (DecodeInstB(MI, insn, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
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@ -37,8 +37,8 @@ def InstB : TestInstruction {
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// CHECK: /* 0 */ MCD::OPC_ExtractField, 4, 4, // Inst{7-4} ...
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// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValue, 0, 14, 0, // Skip to: 21
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// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 2, 2, 0, 5, 0, // Skip to: 18
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// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 27, 0, 0, 0, // Opcode: InstB, skip to: 18
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// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 26, 1, // Opcode: InstA
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// CHECK-NEXT: /* 13 */ MCD::OPC_TryDecode, 28, 0, 0, 0, // Opcode: InstB, skip to: 18
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// CHECK-NEXT: /* 18 */ MCD::OPC_Decode, 27, 1, // Opcode: InstA
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// CHECK-NEXT: /* 21 */ MCD::OPC_Fail,
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// CHECK: if (DecodeInstBOp(MI, tmp, Address, Decoder) == MCDisassembler::Fail) { DecodeComplete = false; return MCDisassembler::Fail; }
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