forked from OSchip/llvm-project
AMDGPU/R600: EXTRACT_VECT_ELT should only bypass BUILD_VECTOR if the vectors have the same number of elements.
Fixes R600 piglit regressions since r280298 Differential Revision: https://reviews.llvm.org/D24174 llvm-svn: 280535
This commit is contained in:
Jan Vesely
parent
6c4140b6c0
commit
ea45746d5a
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@ -1820,7 +1820,9 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
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}
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}
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if (Arg.getOpcode() == ISD::BITCAST &&
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Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR) {
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Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
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(Arg.getOperand(0).getValueType().getVectorNumElements() ==
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Arg.getValueType().getVectorNumElements())) {
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if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
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unsigned Element = Const->getZExtValue();
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return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
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@ -0,0 +1,107 @@
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; This test just checks that the compiler doesn't crash.
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; FUNC-LABEL: {{^}}i8ptr_v16i8ptr:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.XYZW]], [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_128 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]]
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; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @i8ptr_v16i8ptr(<16 x i8> addrspace(1)* %out, i8 addrspace(1)* %in) {
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entry:
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%0 = bitcast i8 addrspace(1)* %in to <16 x i8> addrspace(1)*
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%1 = load <16 x i8>, <16 x i8> addrspace(1)* %0
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store <16 x i8> %1, <16 x i8> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}f32_to_v2i16:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]]
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; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @f32_to_v2i16(<2 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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%load = load float, float addrspace(1)* %in, align 4
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%bc = bitcast float %load to <2 x i16>
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store <2 x i16> %bc, <2 x i16> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v2i16_to_f32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]]
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; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @v2i16_to_f32(float addrspace(1)* %out, <2 x i16> addrspace(1)* %in) nounwind {
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%load = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4
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%bc = bitcast <2 x i16> %load to float
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store float %bc, float addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v4i8_to_i32:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]]
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; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @v4i8_to_i32(i32 addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind {
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%load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
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%bc = bitcast <4 x i8> %load to i32
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store i32 %bc, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}i32_to_v4i8:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]]
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; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @i32_to_v4i8(<4 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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%load = load i32, i32 addrspace(1)* %in, align 4
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%bc = bitcast i32 %load to <4 x i8>
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store <4 x i8> %bc, <4 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v2i16_to_v4i8:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.[XYZW]]], [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_32 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]]
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; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @v2i16_to_v4i8(<4 x i8> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) nounwind {
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%load = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4
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%bc = bitcast <2 x i16> %load to <4 x i8>
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store <4 x i8> %bc, <4 x i8> addrspace(1)* %out, align 4
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ret void
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}
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; This just checks for crash in BUILD_VECTOR/EXTRACT_ELEMENT combine
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; the stack manipulation is tricky to follow
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; TODO: This should only use one load
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; FUNC-LABEL: {{^}}v4i16_extract_i8:
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; EG: MEM_RAT MSKOR {{T[0-9]+\.XW}}, [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_16
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; EG: VTX_READ_16
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; EG-DAG: BFE_UINT
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @v4i16_extract_i8(i8 addrspace(1)* %out, <4 x i16> addrspace(1)* %in) nounwind {
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%load = load <4 x i16>, <4 x i16> addrspace(1)* %in, align 2
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%bc = bitcast <4 x i16> %load to <8 x i8>
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%element = extractelement <8 x i8> %bc, i32 5
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store i8 %element, i8 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}bitcast_v2i32_to_f64:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[DATA:T[0-9]+\.XY]], [[ST_PTR:T[0-9]+\.[XYZW]]]
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; EG: VTX_READ_64 [[DATA]], [[LD_PTR:T[0-9]+\.[XYZW]]]
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; EG-DAG: MOV {{[\* ]*}}[[LD_PTR]], KC0[2].Z
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; EG-DAG: LSHR {{[\* ]*}}[[ST_PTR]], KC0[2].Y, literal
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define void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8
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%bc = bitcast <2 x i32> %val to double
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store double %bc, double addrspace(1)* %out, align 8
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ret void
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}
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@ -0,0 +1,46 @@
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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; XFAIL: *
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; This is the failing part of the r600 bitacts tests
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; TODO: enable doubles
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; FUNC-LABEL: {{^}}bitcast_f64_to_v2i32:
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define void @bitcast_f64_to_v2i32(<2 x i32> addrspace(1)* %out, double addrspace(1)* %in) {
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%val = load double, double addrspace(1)* %in, align 8
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%add = fadd double %val, 4.0
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%bc = bitcast double %add to <2 x i32>
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store <2 x i32> %bc, <2 x i32> addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}bitcast_v2i64_to_v2f64:
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define void @bitcast_v2i64_to_v2f64(i32 %cond, <2 x double> addrspace(1)* %out, <2 x i64> %value) {
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entry:
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%cmp0 = icmp eq i32 %cond, 0
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br i1 %cmp0, label %if, label %end
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if:
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%cast = bitcast <2 x i64> %value to <2 x double>
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br label %end
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end:
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%phi = phi <2 x double> [zeroinitializer, %entry], [%cast, %if]
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store <2 x double> %phi, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}bitcast_v2f64_to_v2i64:
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define void @bitcast_v2f64_to_v2i64(i32 %cond, <2 x i64> addrspace(1)* %out, <2 x double> %value) {
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entry:
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%cmp0 = icmp eq i32 %cond, 0
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br i1 %cmp0, label %if, label %end
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if:
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%cast = bitcast <2 x double> %value to <2 x i64>
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br label %end
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end:
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%phi = phi <2 x i64> [zeroinitializer, %entry], [%cast, %if]
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store <2 x i64> %phi, <2 x i64> addrspace(1)* %out
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ret void
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}
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