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[ARM] Replace ARMISD::VMINNM/VMAXNM with ISD::FMINNUM/FMAXNUM 

NFCI. This replaces another custom ISDNode with a generic equivalent.

llvm-svn: 244591
This commit is contained in:
James Molloy 2015-08-11 12:06:22 +00:00
parent db8ee4b5a9
commit ea3a687a33
4 changed files with 10 additions and 18 deletions
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14
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -932,6 +932,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FTRUNC, MVT::f32, Legal); setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
setOperationAction(ISD::FRINT, MVT::f32, Legal); setOperationAction(ISD::FRINT, MVT::f32, Legal);
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
if (!Subtarget->isFPOnlySP()) { if (!Subtarget->isFPOnlySP()) {
setOperationAction(ISD::FFLOOR, MVT::f64, Legal); setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
setOperationAction(ISD::FCEIL, MVT::f64, Legal); setOperationAction(ISD::FCEIL, MVT::f64, Legal);
@ -939,6 +941,8 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FTRUNC, MVT::f64, Legal); setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
setOperationAction(ISD::FRINT, MVT::f64, Legal); setOperationAction(ISD::FRINT, MVT::f64, Legal);
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
} }
} }
@ -1146,8 +1150,6 @@ const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
case ARMISD::UMLAL: return "ARMISD::UMLAL"; case ARMISD::UMLAL: return "ARMISD::UMLAL";
case ARMISD::SMLAL: return "ARMISD::SMLAL"; case ARMISD::SMLAL: return "ARMISD::SMLAL";
case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR"; case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
case ARMISD::VMAXNM: return "ARMISD::VMAX";
case ARMISD::VMINNM: return "ARMISD::VMIN";
case ARMISD::BFI: return "ARMISD::BFI"; case ARMISD::BFI: return "ARMISD::BFI";
case ARMISD::VORRIMM: return "ARMISD::VORRIMM"; case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
case ARMISD::VBICIMM: return "ARMISD::VBICIMM"; case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
@ -3661,26 +3663,26 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
case ISD::SETOGE: case ISD::SETOGE:
if (!DAG.isKnownNeverNaN(RHS)) if (!DAG.isKnownNeverNaN(RHS))
break; break;
return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS); return DAG.getNode(ISD::FMAXNUM, dl, VT, LHS, RHS);
case ISD::SETUGT: case ISD::SETUGT:
case ISD::SETUGE: case ISD::SETUGE:
if (!DAG.isKnownNeverNaN(LHS)) if (!DAG.isKnownNeverNaN(LHS))
break; break;
case ISD::SETGT: case ISD::SETGT:
case ISD::SETGE: case ISD::SETGE:
return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS); return DAG.getNode(ISD::FMAXNUM, dl, VT, LHS, RHS);
case ISD::SETOLT: case ISD::SETOLT:
case ISD::SETOLE: case ISD::SETOLE:
if (!DAG.isKnownNeverNaN(RHS)) if (!DAG.isKnownNeverNaN(RHS))
break; break;
return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS); return DAG.getNode(ISD::FMINNUM, dl, VT, LHS, RHS);
case ISD::SETULT: case ISD::SETULT:
case ISD::SETULE: case ISD::SETULE:
if (!DAG.isKnownNeverNaN(LHS)) if (!DAG.isKnownNeverNaN(LHS))
break; break;
case ISD::SETLT: case ISD::SETLT:
case ISD::SETLE: case ISD::SETLE:
return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS); return DAG.getNode(ISD::FMINNUM, dl, VT, LHS, RHS);
} }
} }
} }

4
llvm/lib/Target/ARM/ARMISelLowering.h
View File

@ -173,10 +173,6 @@ namespace llvm {
// BUILD_VECTOR for this purpose. // BUILD_VECTOR for this purpose.
BUILD_VECTOR, BUILD_VECTOR,
// Floating-point max and min:
VMAXNM,
VMINNM,
// Bit-field insert // Bit-field insert
BFI, BFI,

6
llvm/lib/Target/ARM/ARMInstrInfo.td
View File

@ -71,9 +71,6 @@ def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; SDTCisVT<2, i32>, SDTCisVT<3, i32>]>;
def SDT_ARMVMAXNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
def SDT_ARMVMINNM : SDTypeProfile<1, 2, [SDTCisFP<0>, SDTCisFP<1>, SDTCisFP<2>]>;
def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
[SDTCisSameAs<0, 2>, [SDTCisSameAs<0, 2>,
SDTCisSameAs<0, 3>, SDTCisSameAs<0, 3>,
@ -180,9 +177,6 @@ def ARMtcret : SDNode<"ARMISD::TC_RETURN", SDT_ARMTCRET,
def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>; def ARMbfi : SDNode<"ARMISD::BFI", SDT_ARMBFI>;
def ARMvmaxnm : SDNode<"ARMISD::VMAXNM", SDT_ARMVMAXNM, []>;
def ARMvminnm : SDNode<"ARMISD::VMINNM", SDT_ARMVMINNM, []>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// ARM Instruction Predicate Definitions. // ARM Instruction Predicate Definitions.
// //

4
llvm/lib/Target/ARM/ARMInstrVFP.td
View File

@ -393,8 +393,8 @@ multiclass vmaxmin_inst<string op, bit opc, SDNode SD> {
} }
} }
defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, ARMvmaxnm>; defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>;
defm VMINNM : vmaxmin_inst<"vminnm", 1, ARMvminnm>; defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>;
// Match reassociated forms only if not sign dependent rounding. // Match reassociated forms only if not sign dependent rounding.
def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)),