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AMDGPU: Fix FP restore from being reordered with stack ops 

In a function, s5 is used as the frame base SGPR. If a function
is calling another function, during the call sequence
it is copied to a preserved SGPR and restored.

Before it was possible for the scheduler to move stack operations
before the restore of s5, since there's nothing to associate
a frame index access with the restore.

Add an implicit use of s5 to the adjcallstack pseudo which ends
the call sequence to preven this from happening. I'm not 100%
satisfied with this solution, but I'm not sure what else would be
better.

llvm-svn: 328650
This commit is contained in:
Matt Arsenault 2018-03-27 18:38:51 +00:00
parent 01c33b8189
commit e9f3679031
2 changed files with 7 additions and 2 deletions
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7
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -3351,8 +3351,13 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
case AMDGPU::ADJCALLSTACKDOWN: { case AMDGPU::ADJCALLSTACKDOWN: {
const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>(); const SIMachineFunctionInfo *Info = MF->getInfo<SIMachineFunctionInfo>();
MachineInstrBuilder MIB(*MF, &MI); MachineInstrBuilder MIB(*MF, &MI);
// Add an implicit use of the frame offset reg to prevent the restore copy
// inserted after the call from being reorderd after stack operations in the
// the caller's frame.
MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine) MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
.addReg(Info->getStackPtrOffsetReg(), RegState::Implicit); .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
.addReg(Info->getFrameOffsetReg(), RegState::Implicit);
return BB; return BB;
} }
case AMDGPU::SI_CALL_ISEL: case AMDGPU::SI_CALL_ISEL:

2
llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll
View File

@ -34,9 +34,9 @@ define amdgpu_kernel void @test_kernel_call_external_void_func_void_clobber_s30_
; GCN: s_mov_b32 s33, s5 ; GCN: s_mov_b32 s33, s5
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
; GCN-NEXT: s_mov_b32 s5, s33 ; GCN-NEXT: s_mov_b32 s5, s33
; GCN-NEXT: s_mov_b32 s33, s5
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN-NEXT: s_mov_b32 s33, s5
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
; GCN-NEXT: s_mov_b32 s5, s33 ; GCN-NEXT: s_mov_b32 s5, s33
; GCN: v_readlane_b32 s37, v32, 4 ; GCN: v_readlane_b32 s37, v32, 4