forked from OSchip/llvm-project
Add some new instructions. Fix the asm string for sbb32rr
llvm-svn: 16759
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2ce32df8b0
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@ -966,19 +966,34 @@ let isTwoAddress = 0 in {
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}
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def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2),
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"adc{l} {$src2, $dst|$dst, $src2}">;
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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let isTwoAddress = 0 in {
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def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2),
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"sbb{b} {$src2, $dst|$dst, $src2}">;
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def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2),
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"sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
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def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2),
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"sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
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def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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}
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def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2),
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"sbb{b} {$src2, $dst|$dst, $src2}">;
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def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2),
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"sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
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def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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def SBB16ri8 : Ii16<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2),
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"sbb{w} {$src2, $dst|$dst, $src2}">, OpSize;
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def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2),
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"sbb{l} {$src2, $dst|$dst, $src2}">;
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@ -124,7 +124,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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#endif
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case X86::ADD16ri: case X86::ADD32ri: case X86::ADC32ri:
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case X86::SUB16ri: case X86::SUB32ri: case X86::SBB32ri:
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case X86::SUB16ri: case X86::SUB32ri:
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case X86::SBB16ri: case X86::SBB32ri:
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case X86::AND16ri: case X86::AND32ri:
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case X86::OR16ri: case X86::OR32ri:
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case X86::XOR16ri: case X86::XOR32ri:
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@ -141,6 +142,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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case X86::ADC32ri: Opcode = X86::ADC32ri8; break;
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case X86::SUB16ri: Opcode = X86::SUB16ri8; break;
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case X86::SUB32ri: Opcode = X86::SUB32ri8; break;
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case X86::SBB16ri: Opcode = X86::SBB16ri8; break;
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case X86::SBB32ri: Opcode = X86::SBB32ri8; break;
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case X86::AND16ri: Opcode = X86::AND16ri8; break;
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case X86::AND32ri: Opcode = X86::AND32ri8; break;
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@ -159,7 +161,8 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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return false;
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case X86::ADD16mi: case X86::ADD32mi: case X86::ADC32mi:
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case X86::SUB16mi: case X86::SUB32mi: case X86::SBB32mi:
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case X86::SUB16mi: case X86::SUB32mi:
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case X86::SBB16mi: case X86::SBB32mi:
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case X86::AND16mi: case X86::AND32mi:
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case X86::OR16mi: case X86::OR32mi:
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case X86::XOR16mi: case X86::XOR32mi:
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@ -176,6 +179,7 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
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case X86::ADC32mi: Opcode = X86::ADC32mi8; break;
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case X86::SUB16mi: Opcode = X86::SUB16mi8; break;
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case X86::SUB32mi: Opcode = X86::SUB32mi8; break;
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case X86::SBB16mi: Opcode = X86::SBB16mi8; break;
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case X86::SBB32mi: Opcode = X86::SBB32mi8; break;
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case X86::AND16mi: Opcode = X86::AND16mi8; break;
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case X86::AND32mi: Opcode = X86::AND32mi8; break;
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@ -178,6 +178,8 @@ MachineInstr* X86RegisterInfo::foldMemoryOperand(MachineInstr* MI,
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case X86::SUB16rr: return MakeMRInst(X86::SUB16mr, FrameIndex, MI);
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case X86::SUB32rr: return MakeMRInst(X86::SUB32mr, FrameIndex, MI);
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case X86::SBB32rr: return MakeMRInst(X86::SBB32mr, FrameIndex, MI);
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case X86::SBB8ri: return MakeMIInst(X86::SBB8mi, FrameIndex, MI);
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case X86::SBB16ri: return MakeMIInst(X86::SBB16mi, FrameIndex, MI);
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case X86::SBB32ri: return MakeMIInst(X86::SBB32mi, FrameIndex, MI);
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case X86::SUB8ri: return MakeMIInst(X86::SUB8mi , FrameIndex, MI);
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case X86::SUB16ri: return MakeMIInst(X86::SUB16mi, FrameIndex, MI);
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