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[AMDGPU] gfx940 basic speed model 

This is incomplete and will handle more instructions as they are added.

Differential Revision: https://reviews.llvm.org/D121966
This commit is contained in:
Stanislav Mekhanoshin 2022-03-17 15:24:00 -07:00
parent 4570527e72
commit e9a49c6483
3 changed files with 33 additions and 2 deletions
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2
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
View File

@ -1688,7 +1688,7 @@ int GCNHazardRecognizer::checkMAIVALUHazards(MachineInstr *MI) {
NeedWaitStates = SMFMA4x4WriteVgprVALUMemExpReadWaitStates;
break;
case 4:
assert(isDGEMM(MFMA->getOpcode()));
assert(isDGEMM(MFMA->getOpcode()) || ST.hasGFX940Insts());
NeedWaitStates =
IsMemOrExport ? DMFMA4x4WriteVgprMemExpReadWaitStates
: DMFMA4x4WriteVgprVALUReadWaitStates;

2
llvm/lib/Target/AMDGPU/GCNProcessors.td
View File

@ -192,7 +192,7 @@ def : ProcessorModel<"gfx90c", SIQuarterSpeedModel,
FeatureISAVersion9_0_C.Features
>;
def : ProcessorModel<"gfx940", SIDPFullSpeedModel,
def : ProcessorModel<"gfx940", SIDPGFX940FullSpeedModel,
FeatureISAVersion9_4_0.Features
>;

31
llvm/lib/Target/AMDGPU/SISchedule.td
View File

@ -59,6 +59,7 @@ def WriteIntMul : SchedWrite;
// mAI multipass instructions.
def Write2PassMAI : SchedWrite;
def Write4PassMAI : SchedWrite;
def Write8PassMAI : SchedWrite;
def Write16PassMAI : SchedWrite;
def Write4PassDGEMM : SchedWrite;
@ -86,6 +87,7 @@ class SISchedMachineModel : SchedMachineModel {
def SIFullSpeedModel : SISchedMachineModel;
def SIQuarterSpeedModel : SISchedMachineModel;
def SIDPFullSpeedModel : SISchedMachineModel;
def SIDPGFX940FullSpeedModel : SISchedMachineModel;
def GFX10SpeedModel : SISchedMachineModel;
// XXX: Are the resource counts correct?
@ -156,6 +158,8 @@ multiclass SICommonWriteRes {
let ResourceCycles = [2] in
def : HWWriteRes<Write2PassMAI, [HWXDL], 2>;
let ResourceCycles = [4] in
def : HWWriteRes<Write4PassMAI, [HWXDL], 4>;
let ResourceCycles = [8] in
def : HWWriteRes<Write8PassMAI, [HWXDL], 8>;
let ResourceCycles = [16] in
@ -244,6 +248,33 @@ def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;
} // End SchedModel = SIDPFullSpeedModel
let SchedModel = SIDPGFX940FullSpeedModel in {
defm : SICommonWriteRes;
def : HWVALUWriteRes<WriteFloatFMA, 1>;
def : HWVALUWriteRes<WriteDouble, 1>;
def : HWVALUWriteRes<WriteDoubleAdd, 1>;
def : HWVALUWriteRes<WriteDoubleCvt, 1>;
def : HWVALUWriteRes<WriteTrans64, 4>;
def : HWVALUWriteRes<WriteIntMul, 1>;
def : HWVALUWriteRes<Write64Bit, 1>;
def : InstRW<[WriteCopy], (instrs COPY)>;
def : InstRW<[Write64Bit], (instregex "^V_ACCVGPR_WRITE_B32_e64$")>;
def : InstRW<[Write2PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_4X4X")>;
def : InstRW<[Write4PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X16")>;
def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_16X16X[14][FBI]")>;
def : InstRW<[Write8PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X8")>;
def : InstRW<[Write16PassMAI, MIMFMARead], (instregex "^V_MFMA_.32_32X32X[124][FBI]")>;
def : InstRW<[Write4PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_4X4X")>;
def : InstRW<[Write8PassDGEMM, MIMFMARead], (instregex "^V_MFMA_.64_16X16X")>;
} // End SchedModel = SIDPGFX940FullSpeedModel
let SchedModel = GFX10SpeedModel in {
// The latency values are 1 / (operations / cycle).