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Do not insert instructions in reverse order. 

llvm-svn: 135464
This commit is contained in:
Akira Hatanaka 2011-07-19 03:14:58 +00:00
parent 1490c6fd8f
commit e97bd81f07
1 changed files with 16 additions and 14 deletions
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30
llvm/lib/Target/Mips/MipsISelLowering.cpp
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@ -917,15 +917,16 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
// sra dest,tmp12,24 // sra dest,tmp12,24
BB = exitMBB; BB = exitMBB;
int64_t ShiftImm = (Size == 1) ? 24 : 16; int64_t ShiftImm = (Size == 1) ? 24 : 16;
// reverse order
BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) MachineBasicBlock::iterator II = BB->begin();
.addReg(Tmp12).addImm(ShiftImm); BuildMI(*BB, II, dl, TII->get(Mips::AND), Tmp10)
BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12)
.addReg(Tmp11).addImm(ShiftImm);
BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11)
.addReg(Tmp10).addReg(Shift);
BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10)
.addReg(Oldval).addReg(Mask); .addReg(Oldval).addReg(Mask);
BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp11)
.addReg(Tmp10).addReg(Shift);
BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp12)
.addReg(Tmp11).addImm(ShiftImm);
BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest)
.addReg(Tmp12).addImm(ShiftImm);
MI->eraseFromParent(); // The instruction is gone now. MI->eraseFromParent(); // The instruction is gone now.
@ -1114,13 +1115,14 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
// sra dest,tmp9,24 // sra dest,tmp9,24
BB = exitMBB; BB = exitMBB;
int64_t ShiftImm = (Size == 1) ? 24 : 16; int64_t ShiftImm = (Size == 1) ? 24 : 16;
// reverse order
BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) MachineBasicBlock::iterator II = BB->begin();
.addReg(Tmp9).addImm(ShiftImm); BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp8)
BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9)
.addReg(Tmp8).addImm(ShiftImm);
BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8)
.addReg(Oldval4).addReg(Shift); .addReg(Oldval4).addReg(Shift);
BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp9)
.addReg(Tmp8).addImm(ShiftImm);
BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest)
.addReg(Tmp9).addImm(ShiftImm);
MI->eraseFromParent(); // The instruction is gone now. MI->eraseFromParent(); // The instruction is gone now.