From e97bd81f074cf3eae8a12678bc11faa712b03983 Mon Sep 17 00:00:00 2001
From: Akira Hatanaka <ahatanak@gmail.com>
Date: Tue, 19 Jul 2011 03:14:58 +0000
Subject: [PATCH] Do not insert instructions in reverse order.

llvm-svn: 135464
---
 llvm/lib/Target/Mips/MipsISelLowering.cpp | 30 ++++++++++++-----------
 1 file changed, 16 insertions(+), 14 deletions(-)

diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 0dd8b065578d..d604a65a685d 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -917,15 +917,16 @@ MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI,
   //    sra     dest,tmp12,24
   BB = exitMBB;
   int64_t ShiftImm = (Size == 1) ? 24 : 16;
-  // reverse order
-  BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest)
-      .addReg(Tmp12).addImm(ShiftImm);
-  BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12)
-      .addReg(Tmp11).addImm(ShiftImm);
-  BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11)
-      .addReg(Tmp10).addReg(Shift);
-  BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10)
+
+  MachineBasicBlock::iterator II = BB->begin();
+  BuildMI(*BB, II, dl, TII->get(Mips::AND), Tmp10)
     .addReg(Oldval).addReg(Mask);
+  BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp11)
+      .addReg(Tmp10).addReg(Shift);
+  BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp12)
+      .addReg(Tmp11).addImm(ShiftImm);
+  BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest)
+      .addReg(Tmp12).addImm(ShiftImm);
 
   MI->eraseFromParent();   // The instruction is gone now.
 
@@ -1114,13 +1115,14 @@ MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI,
   //    sra     dest,tmp9,24
   BB = exitMBB;
   int64_t ShiftImm = (Size == 1) ? 24 : 16;
-  // reverse order
-  BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest)
-      .addReg(Tmp9).addImm(ShiftImm);
-  BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9)
-      .addReg(Tmp8).addImm(ShiftImm);
-  BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8)
+
+  MachineBasicBlock::iterator II = BB->begin();
+  BuildMI(*BB, II, dl, TII->get(Mips::SRL), Tmp8)
       .addReg(Oldval4).addReg(Shift);
+  BuildMI(*BB, II, dl, TII->get(Mips::SLL), Tmp9)
+      .addReg(Tmp8).addImm(ShiftImm);
+  BuildMI(*BB, II, dl, TII->get(Mips::SRA), Dest)
+      .addReg(Tmp9).addImm(ShiftImm);
 
   MI->eraseFromParent();   // The instruction is gone now.