forked from OSchip/llvm-project
[MIPS GlobalISel] Lower uitofp
Add custom lowering for G_UITOFP for MIPS32. Differential Revision: https://reviews.llvm.org/D66930 llvm-svn: 370432
This commit is contained in:
Petar Avramovic
parent
6412b56513
commit
e96892a8aa
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@ -152,6 +152,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder(G_UITOFP)
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.libcallForCartesianProduct({s64, s32}, {s64})
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.customForCartesianProduct({s64, s32}, {s32})
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.minScalar(1, s32);
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getActionDefinitionsBuilder(G_SEXT_INREG).lower();
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@ -168,8 +169,54 @@ bool MipsLegalizerInfo::legalizeCustom(MachineInstr &MI,
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using namespace TargetOpcode;
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MIRBuilder.setInstr(MI);
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const MipsSubtarget &STI =
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static_cast<const MipsSubtarget &>(MIRBuilder.getMF().getSubtarget());
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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return false;
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switch (MI.getOpcode()) {
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case G_UITOFP: {
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Register Dst = MI.getOperand(0).getReg();
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Register Src = MI.getOperand(1).getReg();
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LLT DstTy = MRI.getType(Dst);
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LLT SrcTy = MRI.getType(Src);
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if (SrcTy != s32)
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return false;
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if (DstTy != s32 && DstTy != s64)
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return false;
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// Let 0xABCDEFGH be given unsigned in MI.getOperand(1). First let's convert
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// unsigned to double. Mantissa has 52 bits so we use following trick:
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// First make floating point bit mask 0x43300000ABCDEFGH.
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// Mask represents 2^52 * 0x1.00000ABCDEFGH i.e. 0x100000ABCDEFGH.0 .
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// Next, subtract 2^52 * 0x1.0000000000000 i.e. 0x10000000000000.0 from it.
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// Done. Trunc double to float if needed.
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MachineInstrBuilder Bitcast = MIRBuilder.buildInstr(
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STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64, {s64},
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{Src, MIRBuilder.buildConstant(s32, UINT32_C(0x43300000))});
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Bitcast.constrainAllUses(MIRBuilder.getTII(), *STI.getRegisterInfo(),
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*STI.getRegBankInfo());
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MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
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s64, BitsToDouble(UINT64_C(0x4330000000000000)));
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if (DstTy == s64)
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MIRBuilder.buildFSub(Dst, Bitcast, TwoP52FP);
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else {
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MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
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MIRBuilder.buildFPTrunc(Dst, ResF64);
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}
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MI.eraseFromParent();
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break;
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}
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default:
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return false;
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}
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return true;
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}
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bool MipsLegalizerInfo::legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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@ -12,7 +12,13 @@
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define void @i16tof64() {entry: ret void}
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define void @i8tof64() {entry: ret void}
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define void @u64tof32() {entry: ret void}
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define void @u32tof32() {entry: ret void}
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define void @u16tof32() {entry: ret void}
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define void @u8tof32() {entry: ret void}
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define void @u64tof64() {entry: ret void}
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define void @u32tof64() {entry: ret void}
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define void @u16tof64() {entry: ret void}
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define void @u8tof64() {entry: ret void}
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...
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---
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@ -326,6 +332,124 @@ body: |
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$f0 = COPY %3(s32)
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RetRA implicit $f0
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...
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---
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name: u32tof32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; FP32-LABEL: name: u32tof32
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; FP32: liveins: $a0
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
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; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
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; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
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; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
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; FP32: $f0 = COPY [[FPTRUNC]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: u32tof32
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; FP64: liveins: $a0
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
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; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
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; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
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; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
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; FP64: $f0 = COPY [[FPTRUNC]](s32)
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; FP64: RetRA implicit $f0
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%0:_(s32) = COPY $a0
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%1:_(s32) = G_UITOFP %0(s32)
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: u16tof32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; FP32-LABEL: name: u16tof32
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; FP32: liveins: $a0
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
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; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
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; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
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; FP32: $f0 = COPY [[FPTRUNC]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: u16tof32
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; FP64: liveins: $a0
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
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; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
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; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
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; FP64: $f0 = COPY [[FPTRUNC]](s32)
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; FP64: RetRA implicit $f0
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%1:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s32) = G_UITOFP %0(s16)
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: u8tof32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; FP32-LABEL: name: u8tof32
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; FP32: liveins: $a0
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
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; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
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; FP32: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
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; FP32: $f0 = COPY [[FPTRUNC]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: u8tof32
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; FP64: liveins: $a0
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
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; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
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; FP64: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FSUB]](s64)
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; FP64: $f0 = COPY [[FPTRUNC]](s32)
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; FP64: RetRA implicit $f0
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%1:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %1(s32)
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%2:_(s32) = G_UITOFP %0(s8)
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$f0 = COPY %2(s32)
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RetRA implicit $f0
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...
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---
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name: u64tof64
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@ -367,3 +491,115 @@ body: |
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RetRA implicit $d0
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...
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---
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name: u32tof64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; FP32-LABEL: name: u32tof64
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; FP32: liveins: $a0
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP32: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
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; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[COPY1]], [[C]](s32)
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; FP32: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C1]]
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; FP32: $d0 = COPY [[FSUB]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: u32tof64
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; FP64: liveins: $a0
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[C:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP64: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]](s32)
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; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[COPY1]], [[C]](s32)
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; FP64: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C1]]
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; FP64: $d0 = COPY [[FSUB]](s64)
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; FP64: RetRA implicit $d0
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%0:_(s32) = COPY $a0
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%1:_(s64) = G_UITOFP %0(s32)
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$d0 = COPY %1(s64)
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RetRA implicit $d0
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...
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---
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name: u16tof64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; FP32-LABEL: name: u16tof64
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; FP32: liveins: $a0
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
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; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
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; FP32: $d0 = COPY [[FSUB]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: u16tof64
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; FP64: liveins: $a0
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
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; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
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; FP64: $d0 = COPY [[FSUB]](s64)
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; FP64: RetRA implicit $d0
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%1:_(s32) = COPY $a0
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%0:_(s16) = G_TRUNC %1(s32)
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%2:_(s64) = G_UITOFP %0(s16)
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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---
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name: u8tof64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; FP32-LABEL: name: u8tof64
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; FP32: liveins: $a0
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; FP32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP32: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP32: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP32: [[BuildPairF64_:%[0-9]+]]:afgr64(s64) = BuildPairF64 [[AND]](s32), [[C1]](s32)
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; FP32: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP32: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_]], [[C2]]
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; FP32: $d0 = COPY [[FSUB]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: u8tof64
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; FP64: liveins: $a0
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; FP64: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
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; FP64: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
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; FP64: [[AND:%[0-9]+]]:gpr32(s32) = G_AND [[COPY1]], [[C]]
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; FP64: [[C1:%[0-9]+]]:gpr32(s32) = G_CONSTANT i32 1127219200
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; FP64: [[BuildPairF64_64_:%[0-9]+]]:fgr64(s64) = BuildPairF64_64 [[AND]](s32), [[C1]](s32)
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; FP64: [[C2:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x4330000000000000
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; FP64: [[FSUB:%[0-9]+]]:_(s64) = G_FSUB [[BuildPairF64_64_]], [[C2]]
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; FP64: $d0 = COPY [[FSUB]](s64)
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; FP64: RetRA implicit $d0
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%1:_(s32) = COPY $a0
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%0:_(s8) = G_TRUNC %1(s32)
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%2:_(s64) = G_UITOFP %0(s8)
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$d0 = COPY %2(s64)
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RetRA implicit $d0
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...
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@ -136,6 +136,114 @@ entry:
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ret float %conv
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}
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|
||||
define float @u32tof32(i32 zeroext %a) {
|
||||
; FP32-LABEL: u32tof32:
|
||||
; FP32: # %bb.0: # %entry
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: mtc1 $4, $f0
|
||||
; FP32-NEXT: mtc1 $1, $f1
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: ori $2, $zero, 0
|
||||
; FP32-NEXT: mtc1 $2, $f2
|
||||
; FP32-NEXT: mtc1 $1, $f3
|
||||
; FP32-NEXT: sub.d $f0, $f0, $f2
|
||||
; FP32-NEXT: cvt.s.d $f0, $f0
|
||||
; FP32-NEXT: jr $ra
|
||||
; FP32-NEXT: nop
|
||||
;
|
||||
; FP64-LABEL: u32tof32:
|
||||
; FP64: # %bb.0: # %entry
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: mtc1 $4, $f0
|
||||
; FP64-NEXT: mthc1 $1, $f0
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: ori $2, $zero, 0
|
||||
; FP64-NEXT: mtc1 $2, $f1
|
||||
; FP64-NEXT: mthc1 $1, $f1
|
||||
; FP64-NEXT: sub.d $f0, $f0, $f1
|
||||
; FP64-NEXT: cvt.s.d $f0, $f0
|
||||
; FP64-NEXT: jr $ra
|
||||
; FP64-NEXT: nop
|
||||
entry:
|
||||
%conv = uitofp i32 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
|
||||
define float @u16tof32(i16 zeroext %a) {
|
||||
; FP32-LABEL: u16tof32:
|
||||
; FP32: # %bb.0: # %entry
|
||||
; FP32-NEXT: ori $1, $zero, 65535
|
||||
; FP32-NEXT: and $1, $4, $1
|
||||
; FP32-NEXT: lui $2, 17200
|
||||
; FP32-NEXT: mtc1 $1, $f0
|
||||
; FP32-NEXT: mtc1 $2, $f1
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: ori $2, $zero, 0
|
||||
; FP32-NEXT: mtc1 $2, $f2
|
||||
; FP32-NEXT: mtc1 $1, $f3
|
||||
; FP32-NEXT: sub.d $f0, $f0, $f2
|
||||
; FP32-NEXT: cvt.s.d $f0, $f0
|
||||
; FP32-NEXT: jr $ra
|
||||
; FP32-NEXT: nop
|
||||
;
|
||||
; FP64-LABEL: u16tof32:
|
||||
; FP64: # %bb.0: # %entry
|
||||
; FP64-NEXT: ori $1, $zero, 65535
|
||||
; FP64-NEXT: and $1, $4, $1
|
||||
; FP64-NEXT: lui $2, 17200
|
||||
; FP64-NEXT: mtc1 $1, $f0
|
||||
; FP64-NEXT: mthc1 $2, $f0
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: ori $2, $zero, 0
|
||||
; FP64-NEXT: mtc1 $2, $f1
|
||||
; FP64-NEXT: mthc1 $1, $f1
|
||||
; FP64-NEXT: sub.d $f0, $f0, $f1
|
||||
; FP64-NEXT: cvt.s.d $f0, $f0
|
||||
; FP64-NEXT: jr $ra
|
||||
; FP64-NEXT: nop
|
||||
entry:
|
||||
%conv = uitofp i16 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
|
||||
define float @u8tof32(i8 zeroext %a) {
|
||||
; FP32-LABEL: u8tof32:
|
||||
; FP32: # %bb.0: # %entry
|
||||
; FP32-NEXT: ori $1, $zero, 255
|
||||
; FP32-NEXT: and $1, $4, $1
|
||||
; FP32-NEXT: lui $2, 17200
|
||||
; FP32-NEXT: mtc1 $1, $f0
|
||||
; FP32-NEXT: mtc1 $2, $f1
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: ori $2, $zero, 0
|
||||
; FP32-NEXT: mtc1 $2, $f2
|
||||
; FP32-NEXT: mtc1 $1, $f3
|
||||
; FP32-NEXT: sub.d $f0, $f0, $f2
|
||||
; FP32-NEXT: cvt.s.d $f0, $f0
|
||||
; FP32-NEXT: jr $ra
|
||||
; FP32-NEXT: nop
|
||||
;
|
||||
; FP64-LABEL: u8tof32:
|
||||
; FP64: # %bb.0: # %entry
|
||||
; FP64-NEXT: ori $1, $zero, 255
|
||||
; FP64-NEXT: and $1, $4, $1
|
||||
; FP64-NEXT: lui $2, 17200
|
||||
; FP64-NEXT: mtc1 $1, $f0
|
||||
; FP64-NEXT: mthc1 $2, $f0
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: ori $2, $zero, 0
|
||||
; FP64-NEXT: mtc1 $2, $f1
|
||||
; FP64-NEXT: mthc1 $1, $f1
|
||||
; FP64-NEXT: sub.d $f0, $f0, $f1
|
||||
; FP64-NEXT: cvt.s.d $f0, $f0
|
||||
; FP64-NEXT: jr $ra
|
||||
; FP64-NEXT: nop
|
||||
entry:
|
||||
%conv = uitofp i8 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
|
||||
define double @u64tof64(i64 zeroext %a) {
|
||||
; MIPS32-LABEL: u64tof64:
|
||||
; MIPS32: # %bb.0: # %entry
|
||||
|
|
@ -153,3 +261,104 @@ entry:
|
|||
%conv = uitofp i64 %a to double
|
||||
ret double %conv
|
||||
}
|
||||
|
||||
define double @u32tof64(i32 zeroext %a) {
|
||||
; FP32-LABEL: u32tof64:
|
||||
; FP32: # %bb.0: # %entry
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: mtc1 $4, $f0
|
||||
; FP32-NEXT: mtc1 $1, $f1
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: ori $2, $zero, 0
|
||||
; FP32-NEXT: mtc1 $2, $f2
|
||||
; FP32-NEXT: mtc1 $1, $f3
|
||||
; FP32-NEXT: sub.d $f0, $f0, $f2
|
||||
; FP32-NEXT: jr $ra
|
||||
; FP32-NEXT: nop
|
||||
;
|
||||
; FP64-LABEL: u32tof64:
|
||||
; FP64: # %bb.0: # %entry
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: mtc1 $4, $f0
|
||||
; FP64-NEXT: mthc1 $1, $f0
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: ori $2, $zero, 0
|
||||
; FP64-NEXT: mtc1 $2, $f1
|
||||
; FP64-NEXT: mthc1 $1, $f1
|
||||
; FP64-NEXT: sub.d $f0, $f0, $f1
|
||||
; FP64-NEXT: jr $ra
|
||||
; FP64-NEXT: nop
|
||||
entry:
|
||||
%conv = uitofp i32 %a to double
|
||||
ret double %conv
|
||||
}
|
||||
|
||||
define double @u16tof64(i16 zeroext %a) {
|
||||
; FP32-LABEL: u16tof64:
|
||||
; FP32: # %bb.0: # %entry
|
||||
; FP32-NEXT: ori $1, $zero, 65535
|
||||
; FP32-NEXT: and $1, $4, $1
|
||||
; FP32-NEXT: lui $2, 17200
|
||||
; FP32-NEXT: mtc1 $1, $f0
|
||||
; FP32-NEXT: mtc1 $2, $f1
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: ori $2, $zero, 0
|
||||
; FP32-NEXT: mtc1 $2, $f2
|
||||
; FP32-NEXT: mtc1 $1, $f3
|
||||
; FP32-NEXT: sub.d $f0, $f0, $f2
|
||||
; FP32-NEXT: jr $ra
|
||||
; FP32-NEXT: nop
|
||||
;
|
||||
; FP64-LABEL: u16tof64:
|
||||
; FP64: # %bb.0: # %entry
|
||||
; FP64-NEXT: ori $1, $zero, 65535
|
||||
; FP64-NEXT: and $1, $4, $1
|
||||
; FP64-NEXT: lui $2, 17200
|
||||
; FP64-NEXT: mtc1 $1, $f0
|
||||
; FP64-NEXT: mthc1 $2, $f0
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: ori $2, $zero, 0
|
||||
; FP64-NEXT: mtc1 $2, $f1
|
||||
; FP64-NEXT: mthc1 $1, $f1
|
||||
; FP64-NEXT: sub.d $f0, $f0, $f1
|
||||
; FP64-NEXT: jr $ra
|
||||
; FP64-NEXT: nop
|
||||
entry:
|
||||
%conv = uitofp i16 %a to double
|
||||
ret double %conv
|
||||
}
|
||||
|
||||
define double @u8tof64(i8 zeroext %a) {
|
||||
; FP32-LABEL: u8tof64:
|
||||
; FP32: # %bb.0: # %entry
|
||||
; FP32-NEXT: ori $1, $zero, 255
|
||||
; FP32-NEXT: and $1, $4, $1
|
||||
; FP32-NEXT: lui $2, 17200
|
||||
; FP32-NEXT: mtc1 $1, $f0
|
||||
; FP32-NEXT: mtc1 $2, $f1
|
||||
; FP32-NEXT: lui $1, 17200
|
||||
; FP32-NEXT: ori $2, $zero, 0
|
||||
; FP32-NEXT: mtc1 $2, $f2
|
||||
; FP32-NEXT: mtc1 $1, $f3
|
||||
; FP32-NEXT: sub.d $f0, $f0, $f2
|
||||
; FP32-NEXT: jr $ra
|
||||
; FP32-NEXT: nop
|
||||
;
|
||||
; FP64-LABEL: u8tof64:
|
||||
; FP64: # %bb.0: # %entry
|
||||
; FP64-NEXT: ori $1, $zero, 255
|
||||
; FP64-NEXT: and $1, $4, $1
|
||||
; FP64-NEXT: lui $2, 17200
|
||||
; FP64-NEXT: mtc1 $1, $f0
|
||||
; FP64-NEXT: mthc1 $2, $f0
|
||||
; FP64-NEXT: lui $1, 17200
|
||||
; FP64-NEXT: ori $2, $zero, 0
|
||||
; FP64-NEXT: mtc1 $2, $f1
|
||||
; FP64-NEXT: mthc1 $1, $f1
|
||||
; FP64-NEXT: sub.d $f0, $f0, $f1
|
||||
; FP64-NEXT: jr $ra
|
||||
; FP64-NEXT: nop
|
||||
entry:
|
||||
%conv = uitofp i8 %a to double
|
||||
ret double %conv
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue